Author Topic: How far away would you place your bypass caps before you considered a problem?  (Read 4504 times)

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Offline NaDobraNichTopic starter

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I’m laying out in stm32 part, using up some excess inventory on the side project.

https://www.st.com/resource/en/datasheet/stm32h725ie.pdf

No ADC, no DAC, just some digital UART, SPI, IO, USB, Ethernet. It’s a BGA package, 176+25. Plan to run 260Mhz or so.

I don’t have a great access to the bottom of the board. Not enough to put the bypass caps as close to the pins as I would like. This part needs like 13x 100nF and another 6x various for the internal LDO and etc. I can got down to 0401 and 0201 parts.

How far away would you route these before getting concerned?

In an ideal world, I think I can get the traces to be about 1mm with via.  Would 4mm be OK? 6mm? I know there is no hard answer here, just gut, how far would until it’s an issue?
« Last Edit: September 23, 2023, 01:41:41 am by NaDobraNich »
 

Online uer166

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Presumably the die in the BGA is the same as the LQFP parts which are very large. The internal lead frame and bond wires are likely quite far from the die, and have no magical properties vs. traces on a PCB. I suspect you'll be okay placing all decoupling at the periphery of the BGA, just prioritize them and you'll probably be ok on emissions with a good stack up.
 
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Offline NaDobraNichTopic starter

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… how have I never thought about it like that!

I agree, the die probably is the same, and it’s just wires to it…. Huh.

I can get most on the bottom nicely but some would have to be a little longer and it was bugging me.
 

Offline NaDobraNichTopic starter

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So thinking about it a little, if you had a high power usage, that the BGA parts should preform “better” than the large LQFP parts in terms of how much closer you can get the bypass caps? Does anyone recommend BGA parts for that reason? I’ve never seen it.

The alternative is that 10mm isn’t going to hurt anything very little of it matters despite being a large topic of discussion.
 

Offline Psi

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Have you considered capacitor array packages. The kind that have like 4 caps in one package.
They cost more, but are a little smaller.
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Online dietert1

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As there are many unknowns in this i would have a look at the STM32 evaluation boards with this or a similar MCU and try to learn from that. If you have one of those boards you could also measure how much noise appears on the external buffer caps. Using a spectrum analyzer, you can probably see the clocks and some capacitor resonances. I'd assume there are small buffer caps on chip and the spectrum should level off at some frequency (like 50 or 100 MHz).

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Offline Silenos

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So thinking about it a little, if you had a high power usage, that the BGA parts should preform “better” than the large LQFP parts in terms of how much closer you can get the bypass caps? Does anyone recommend BGA parts for that reason? I’ve never seen it.
If it is just for power the designs are propably optimized around it and packages. If you use proper +4 layers stackup, you should be fine - I saw 2 layers boards with old stm32f1 were noisy. You mentioned eth - I would take that eth phy is more layout demanding and noisier when it comes to power transients than your bga h7.
It may starts mattering around the LDO or those integrated dc-dc converters, see the ANs. Also packages matter with ADC/DAC performance, see eg an5354.
 

Online peter-h

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The answer obviously depends on the chip which specifies them.

There are two reasons for these caps

1) to supply transient current demands without an excessive Vcc dip
2) to ensure stability of (typically LDO) voltage regulators

On 1), if you go back say 20-30 years, 4+ layer PCBs were rare and expensive, so people used 2 layer and because the supply rails were just thin tracks, you peppered the board with decoupling caps. With 4 layer boards (inner layers being GND and VCC) this is far less critical. Also modern digital boards rarely are just hundreds of logic gate chips (74HC240 etc); you tend to have a CPU and a few other chips, so putting caps close to them is not a problem.

On 2), the distance does not usually matter but if a given LDO, say LM2940CT-5.0, says this



then you have to provide that capacitance.
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Online nctnico

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I'd follow the appnote of the manufacturer of the chip to be sure. IOW: read the manual.  8)
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline NaDobraNichTopic starter

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There’s really no need to read the datasheet on this.

This is exactly what you’d expect and we’ve all seen hundred or thousand times:

Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

What I’m trying to figure out is when is it too much?

It’ll be a 6 or 8 layer board, and the power and ground layers are very close to each other.

On my design, I have some that are about 3-4 mm away because of other bottom side components that I can’t move. I’m pretty sure it’s not going to be a problem, but that’s why I am asking.
 

Offline Nominal Animal

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What I’m trying to figure out is when is it too much?
There is no way to determine the limit beforehand, because it depends on the entire circuit and the supply.  After all, IC's tend to consume current in spikes, and the bypass capacitors are intended to act as local reservoirs so that the voltage stays reasonably stable without dipping and causing errors.  The amount of capacitance needed depends on those spikes, and the distance affects how fast the capacitor reacts.

Some circuits even keep working when you remove some/most of the 'required' bypass caps entirely.

If you examine existing boards and designs, you'll see both 1µF and 100nF ceramic capacitors of the same type in parallel, next to each other, on the same supply pin –– even though the 100nF of the same ceramic type is utterly useless there.  In other words, because there is no easy to verify rules, people rely on rules of thumb, and tend to not think about it.
 
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Online nctnico

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What I’m trying to figure out is when is it too much?
There is no way to determine the limit beforehand, because it depends on the entire circuit and the supply.  After all, IC's tend to consume current in spikes, and the bypass capacitors are intended to act as local reservoirs so that the voltage stays reasonably stable without dipping and causing errors.  The amount of capacitance needed depends on those spikes, and the distance affects how fast the capacitor reacts.

Some circuits even keep working when you remove some/most of the 'required' bypass caps entirely.

If you examine existing boards and designs, you'll see both 1µF and 100nF ceramic capacitors of the same type in parallel, next to each other, on the same supply pin –– even though the 100nF of the same ceramic type is utterly useless there.  In other words, because there is no easy to verify rules, people rely on rules of thumb, and tend to not think about it.
The 100nf isn't useless at all. Do some measurements with a network analyser and you'll see why. For really high frequency stuff, it is even useful to put a 10nf or even a 1nf in parallel. A higher value capacitor will have a lower self resonance frequency after which the impedance rises up again. So with several values in parallel using the same package size, you get a low impedance from your power supply network over a wider frequency range.

There’s really no need to read the datasheet on this.
Indeed, you need to read the application notes / reference designs to get an idea about what is critical and what is not. The datasheet is not the place to look for circuit application information. Heck, many of the circuits shows in datasheets won't lead to a product you can sell.
« Last Edit: September 25, 2023, 11:25:53 am by nctnico »
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Offline Someone

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What I’m trying to figure out is when is it too much?
There is no way to determine the limit beforehand, because it depends on the entire circuit and the supply.  After all, IC's tend to consume current in spikes, and the bypass capacitors are intended to act as local reservoirs so that the voltage stays reasonably stable without dipping and causing errors.  The amount of capacitance needed depends on those spikes, and the distance affects how fast the capacitor reacts.

Some circuits even keep working when you remove some/most of the 'required' bypass caps entirely.

If you examine existing boards and designs, you'll see both 1µF and 100nF ceramic capacitors of the same type in parallel, next to each other, on the same supply pin –– even though the 100nF of the same ceramic type is utterly useless there.  In other words, because there is no easy to verify rules, people rely on rules of thumb, and tend to not think about it.
The 100nf isn't useless at all. Do some measurements with a network analyser and you'll see why. For really high frequency stuff, it is even useful to put a 10nf or even a 1nf in parallel.
Still playing your game of saying technically true and inflammatory things by omission?

Parasitics are what cause resonances, not the capacitance values alone. In real world uses when comparing the same case size as you would for 1n 10n 100n and 1uF the largest capacitance is almost always the optimal choice.
https://www.eevblog.com/forum/projects/decoupling-caps-value/?all
 
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Online nctnico

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I guess you never measured the effect of having several capacitors with different values (same case size) in parallel using a network analyser. I have but the thread you are referring to shows no measurement data at all. Just a lot of guess work.
« Last Edit: September 25, 2023, 10:15:50 pm by nctnico »
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Offline SiliconWizard

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Just compare the ESR and ESL of 1uF, 100nF, 10nF, 1nF caps in the same package.
Now if one puts a 1uF cap in say 0402 and a 1nF cap in 0201 or 01005 in parallel, you will (marginally) improve the frequency response at very high frequencies.
But for small ceramic caps it's more about the package itself than the capacitance, so it's more about putting a smaller package cap in parallel rather than the capacitance itself (just that you have less chance of finding a larger capacitance in a smaller package.)
 
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Offline Someone

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The 100nf isn't useless at all. Do some measurements with a network analyser and you'll see why. For really high frequency stuff, it is even useful to put a 10nf or even a 1nf in parallel.
Still playing your game of saying technically true and inflammatory things by omission?

Parasitics are what cause resonances, not the capacitance values alone. In real world uses when comparing the same case size as you would for 1n 10n 100n and 1uF the largest capacitance is almost always the optimal choice.
https://www.eevblog.com/forum/projects/decoupling-caps-value/?all
I guess you never measured the effect of having several capacitors with different values (same case size) in parallel using a network analyser. I have but the thread you are referring to shows no measurement data at all. Just a lot of guess work.
Well done throwing shade rather than any support of your position....

I have measured PDN impedance with a range of instruments, including VNAs. But they aren't nessecary for the scalar impedance as a recent example shows:
https://jmw.name/projects/exploring-pdns/
Neatly answering the OPs question directly.

Adding disparate capacitance values in parallel (of the same case size) is usually a bad idea, tiny gains at resonant frequencies being offset by loss at anti-resonances. Having run optimisation on capacitance selection and placement the general solution is: start with the smallest case size practical adding in a bunch of those at the largest economic capacitance until the highest frequency constraint is met, then add some much larger capacitance size+value (100x-1000x step) until that cant practically improve the result. I'm yet to see a real application where that worked less well or was more expensive than the finely distributed values approach.

These sorts of "rules" need to pointed out for the overly simplified crap they are, parroted and argued about without actually mentioning the how's/why's/limitations.
 
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Offline westfw

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There is no way to determine the limit beforehand
Presumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor.  But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)!  Of course RLC issues would make the distance shorter.
 
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Offline SL4P

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My personal rule of thumb is around 10mm from the pin.
Don't ask a question if you aren't willing to listen to the answer.
 
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Offline NaDobraNichTopic starter

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My personal rule of thumb is around 10mm from the pin.

It seems ST would agree with you.

Some of their reference designs have an LCD opposite of the BGA so they use single side components, and in that case all of their caps are ~10mm, usually just fortifying the ground plane all around the chip. Then the chip ties into the planes as well. I’ll still try and beat that, but now I know that 4-6mm isn’t going to kill me.
 

Offline Nominal Animal

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There is no way to determine the limit beforehand
Presumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor.  But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)!  Of course RLC issues would make the distance shorter.
The RLC issues including the inherent capacitance, inductance, and resistance of the PCB traces themselves, and even in the bond wires inside the ICs.
So yeah, it is modelable and theoretically computable; but no software package or mathematical rules of thumb or even theoretical models exist, for one to predict the exact capacitances and maximum distances one needs for the circuit to work –– except via practical experimentation.

Perhaps I should have written no practical way, but I am not aware of any theoretical framework for determining such limits either: even if it is theoretically possible to compute such a limit, it would be extremely complex and require much more information than normally available to circuit designers, and end up being much more work than experimenting with the said ICs in practice to find out their typical bypass capacitor needs and distance limits.

This is one field where practical experimentation rules.  But it is not just about finding the minimum sufficient limit, but also about taking into consideration the aging of the capacitors, and the bias voltage affecting the effective capacitance wrt. noise or signal on top of the DC bias.  Rules of thumb like "double the minimum" are common, as are all sorts of weird beliefs based on specific special corner cases, so one will just have to wade through the bypass capacitor fud mud being slung everywhere, and find the stable ground underneath for yourself.

Remember this about those who claim to be an authority: At one point, doctors and surgeons refused to wash their hands, because they obviously were doing good work, and the idea of them conveying a disease via their hands was simply completely unacceptable.
 

Online nctnico

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The 100nf isn't useless at all. Do some measurements with a network analyser and you'll see why. For really high frequency stuff, it is even useful to put a 10nf or even a 1nf in parallel.
Still playing your game of saying technically true and inflammatory things by omission?

Parasitics are what cause resonances, not the capacitance values alone. In real world uses when comparing the same case size as you would for 1n 10n 100n and 1uF the largest capacitance is almost always the optimal choice.
https://www.eevblog.com/forum/projects/decoupling-caps-value/?all
I guess you never measured the effect of having several capacitors with different values (same case size) in parallel using a network analyser. I have but the thread you are referring to shows no measurement data at all. Just a lot of guess work.
Well done throwing shade rather than any support of your position....

I have measured PDN impedance with a range of instruments, including VNAs. But they aren't nessecary for the scalar impedance as a recent example shows:
https://jmw.name/projects/exploring-pdns/
This link just proves my point: if you parallel capacitors of different values, you'll get a low impedance over a wider frequency range.  :palm: But there are several omissions by the author of that web page (trying to use the parallel plate formula to calculate capacitance from a board without taking fringe effects into account and the sub-optimal board layout used for the measurement are clear signs) so take the conclusions with a pinch of salt.
« Last Edit: September 26, 2023, 07:48:55 am by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online tszaboo

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Quote
There is no way to determine the limit beforehand
Presumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor.  But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)!  Of course RLC issues would make the distance shorter.
But usually the caps are not there to filter the clock frequency. In fact, for a logic chip, the clock frequency doesn't matter much, it's the slew rate that matters. Sure you will get a little noise due to the internal switching but most of the noise is coming from the pins switching.

All: TBH I don't like these anecdotes on engineering forums outside the beginners section. Have you looked at your power delivery network with any measurement tool? Have you simulated it? Have you recorded eye diagrams? And have you sent your device through EMC or RED certification? Those measure up to 70GHz in the new RED.
Something working is very different from something properly designed.

Just compare the ESR and ESL of 1uF, 100nF, 10nF, 1nF caps in the same package.
Now if one puts a 1uF cap in say 0402 and a 1nF cap in 0201 or 01005 in parallel, you will (marginally) improve the frequency response at very high frequencies.
But for small ceramic caps it's more about the package itself than the capacitance, so it's more about putting a smaller package cap in parallel rather than the capacitance itself (just that you have less chance of finding a larger capacitance in a smaller package.)
Yes, this absolutely. I've been stuck with 0402 for one reason or another for a while now, and it's really a struggle to make good layout. On my last layout I had to place the bypassing up to 1.5mm from the pins of a micro, because everything is in the way. I already don't like the idea to go to the RED certification.
 

Offline tggzzz

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Quote
There is no way to determine the limit beforehand
Presumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor.  But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)!  Of course RLC issues would make the distance shorter.
But usually the caps are not there to filter the clock frequency. In fact, for a logic chip, the clock frequency doesn't matter much, it's the slew rate that matters. Sure you will get a little noise due to the internal switching but most of the noise is coming from the pins switching.

Exactly.

In pessimal designs the clock frequency will match the anti-parallel resonant peak impedance (oops!) :)

Quote
All: TBH I don't like these anecdotes on engineering forums outside the beginners section. Have you looked at your power delivery network with any measurement tool? Have you simulated it? Have you recorded eye diagrams? And have you sent your device through EMC or RED certification? Those measure up to 70GHz in the new RED.
Something working is very different from something properly designed.

Design is so.... old fashioned. As long as it passes the tests (i.e. in Test Driven Development), it works - by definition. (Yes Virginia, nowadays you can inspect/test quality into a product. Not.)

More sensibly testing is used to confirm the unit is working as designed.

Quote
Just compare the ESR and ESL of 1uF, 100nF, 10nF, 1nF caps in the same package.
Now if one puts a 1uF cap in say 0402 and a 1nF cap in 0201 or 01005 in parallel, you will (marginally) improve the frequency response at very high frequencies.
But for small ceramic caps it's more about the package itself than the capacitance, so it's more about putting a smaller package cap in parallel rather than the capacitance itself (just that you have less chance of finding a larger capacitance in a smaller package.)
Yes, this absolutely. I've been stuck with 0402 for one reason or another for a while now, and it's really a struggle to make good layout. On my last layout I had to place the bypassing up to 1.5mm from the pins of a micro, because everything is in the way. I already don't like the idea to go to the RED certification.

There is a reason 0306 capacitors exist: lower package inductance than 0603 capacitors. I'm sure you knew that ;)
« Last Edit: September 26, 2023, 10:45:42 am by tggzzz »
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Online nctnico

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Quote
There is no way to determine the limit beforehand
Presumably there is a hard limit imposed by physics if the clock period of the device gets significantly close to the speed-of-light-in-copper delay of current from the capacitor.  But that's pretty far away (I get 1cm should be OK for up to about ~20GHz)!  Of course RLC issues would make the distance shorter.
The RLC issues including the inherent capacitance, inductance, and resistance of the PCB traces themselves, and even in the bond wires inside the ICs.
So yeah, it is modelable and theoretically computable; but no software package or mathematical rules of thumb or even theoretical models exist, for one to predict the exact capacitances and maximum distances one needs for the circuit to work –– except via practical experimentation.

Perhaps I should have written no practical way, but I am not aware of any theoretical framework for determining such limits either: even if it is theoretically possible to compute such a limit, it would be extremely complex and require much more information than normally available to circuit designers, and end up being much more work than experimenting with the said ICs in practice to find out their typical bypass capacitor needs and distance limits.
You are aware that the higher end PCB CAD packages offer DC and AC power distribution network analysis? In addition to that, chips running at high frequencies (like SoCs) have specifications in their hardware manuals that say what kind of DC resistance and AC impedance (typically specified at several frequency ranges) the chip requires on the various supply pins in order to work. There really isn't any need for magic or experimentation. You can at least measure it to verify your board design. Even a cheap NanoVNA (at least a version with a decent dynamic range) can get you quite far for doing HF PDN measurements.


And simulating DC resistance using free tools isn't out of the question. Recently I came across this video:
« Last Edit: September 26, 2023, 03:11:04 pm by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online uer166

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In general paralleling caps of different values but of same case size results in a higher PDN impedance over the frequency range, vs just using the maximum possible values.

You don't need a VNA to realize that, just look at capacitor impedance plots in KSIM and such. Of course I have observed that via measurements as well.. Some of the above comments imply that somehow a cap stops working above self-resonance which is bs. The absolute impedance is what matters, not whether the cap "looks" like an inductor or not.

Anti-resonance is a real effect as well, and you need to do actual PDN design to avoid it (i.e. it's not just throwing a couple caps of different values together). In practice that means many different cases sizes, closely spaced nominal values, and highly optimized layout. Nothing to do with OP's problem of decoupling an MCU designed for a 1inchx1inch TQFP.
 
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