Electronics > Microcontrollers

How far away would you place your bypass caps before you considered a problem?

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temperance:

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--- Quote ---What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB.  Datasheets never give impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.
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See my earlier post on typical modern 32Bit controllers. They have an on board LDO and decoupling is done on chip. Some older chips require a capacitor on the outside for stability while some don't require an external capacitor.

The external decoupling is more required for:
-The input of the LDO. (but not much information is given very often.)
-The transient current (di/dt) required by what has been connected to the GPIO pins.


--- Quote ---Even the most trivial specs, manufacturers never provide -- consider the capacitance of VDD to GND alone!  This is so easily measured, you can do it yourself; I'd be willing to bet you'll find many large-ish MCUs in the ~uF range.  Now that would be some interesting (and useful) context for PDN design, wouldn't it?
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Only the LDO is messing up your measurement for most 32bit micros.

nctnico:

--- Quote from: T3sl4co1l on September 27, 2023, 09:50:38 pm ---
--- Quote from: nctnico on September 27, 2023, 08:59:41 pm ---That goes without saying  :) But the way you accomplish the impedance getting low enough is the million dollar question. At some point you simply run out of room to add more 10uf capacitors around a BGA package (not to mention leaving room for traces). So what to do then?

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What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB.  Datasheets never give impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.

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For microcontrollers such info is typically missing in the datasheet but you might be able to find an appnote (unless putting a 100nf capacitor withing a few mm of the power pin will just work). Whatever could be perceived as a hindrance to design a component in, gets burried in an application note. For SoCs the power impedance requirements are very well specified; but this info is in the hardware manual or an application note. BTW: If you want to see an interesting appnote on power supply routing & decoupling, get the hardware manual for the ESP32-S3  :) They use the trace impedance to seperate the various analog and digital power supplies.

Someone:

--- Quote from: Zero999 on September 27, 2023, 06:21:53 pm ---You're right that it's generally better to use a single, large capacitor, rather than several smaller ones. It doesn't matter if it has a lower self-resonant frequency. It will have a lower impedance at higher frequencies, simply because it has a lower ESR.
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I'm specifically not saying that, and framed the situation of a given number of (possibly specifically physically sized) capacitances. Through all this noise the important point keeps getting pushed away.

If you had a choice of capacitance in a given footprint, almost universally the larger capacitance produces the better result.

Which is far more practical than the "spread out capacitance values to have resonances everywhere" that keeps getting parroted. Trace and case parasitics are the dominant limitation to high frequency decoupling, which is what the OP asked about. So I'm trying to cut through all the rubbish here and point people to contemporary and accurate content on that. But a certain member has taken it upon themselves to attack anyone else's discussion on the matter, walking the goalposts way off into troll land.

temperance:

--- Quote ---Through all this noise the important point keeps getting pushed away.
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An other important point missing is this discussion is that the PCB layout becomes very critical of you want to keep the PDN impedance below that of a small MLCC. It's better to take a very close look at the PCB layout than looking at infinitum into the impedance offered by some MLCC caps. After all, a BGA has only a limited number of GND and VCC connections for which you need a bunch of VIA's measuring about 1 nH each.

nctnico:

--- Quote from: temperance on September 27, 2023, 10:33:40 pm ---
--- Quote ---Through all this noise the important point keeps getting pushed away.
--- End quote ---

An other important point missing is this discussion is that the PCB layout becomes very critical of you want to keep the PDN impedance below that of a small MLCC. It's better to take a very close look at the PCB layout than looking at infinitum into the impedance offered by some MLCC caps. After all, a BGA has only a limited number of GND and VCC connections for which you need a bunch of VIA's measuring about 1 nH each.

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Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).

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