Electronics > Microcontrollers

How far away would you place your bypass caps before you considered a problem?

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Simon:

--- Quote from: NaDobraNich on September 24, 2023, 04:22:02 am ---So thinking about it a little, if you had a high power usage, that the BGA parts should preform “better” than the large LQFP parts in terms of how much closer you can get the bypass caps? Does anyone recommend BGA parts for that reason? I’ve never seen it.

The alternative is that 10mm isn’t going to hurt anything very little of it matters despite being a large topic of discussion.

--- End quote ---

I think it's price mostly Capacitance is physical, you can't wish it into a smaller space so making tiny silicon and then asking for a ton of bypass capacitance will not magically make it happen. I have never worked on anything with so many caps. What I tend to use is a micro controller where a 100nF is recommended on each power pin, on a 64VQFN this is a challenge as a analogue supply and digital supply pins are next to each other. Obviously on 0.5mm pitch you won't get the cap sideways to get positive rail and GND close to the chip. So I end up pointing the positive to the chip and rely on the ground plane to not have much inductance. They then recommend something ridiculous like 10µF on each rail, I don't even try to get these close, it's impossible with a 1206-1812 part size. I think these are desirable mainly as bulk capacitance on steroids ESR wise and are more for arse covering purposes, so I don't fuss too much about them. Generally they go behind one of the smaller ones on the same rail.

temperance:

--- Quote ---Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).
--- End quote ---

The idea for the kind of PDN you are thinking about is to keep the impedance as constant as possible because any peak or valley is responsible for noise on the PDN network even if those peaks are below the required PDN impedance.

A tough subject on its own for which you will need pretty expensive software and equipment to verify final product performance. Did NXP go so far to develop a dev board? Maybe you can ask them or connect a network analyzer to the dev board if you've got one and post the result here.

Is it a good idea to follow the dev board schematic? No if the PDN on your own board is different.

nctnico:

--- Quote from: temperance on September 28, 2023, 10:30:04 am ---
--- Quote ---Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).
--- End quote ---

The idea for the kind of PDN you are thinking about is to keep the impedance as constant as possible because any peak or valley is responsible for noise on the PDN network even if those peaks are below the required PDN impedance.

A tough subject on its own for which you will need pretty expensive software and equipment to verify final product performance. Did NXP go so far to develop a dev board?

--- End quote ---
I think they went this far. Typically these evaluation boards from serious manufacturers (like NXP, NVidia, TI) are used as golden standards. If you ask support to help fixing a problem using your own design, their first reply is to try and replicate the problem on their reference design. Getting access to some form of board level AC power integrity simulation for my own designs is high on my list though.


--- Quote ---Maybe you can ask them or connect a network analyzer to the dev board if you've got one and post the result here.

--- End quote ---
I have an IMX8MQ eval board so I hooked it up to my LF network analyser for a (crude) S21 shunt measurement for the memory supply (which is amongst the more critical supplies):


This is from a IMX8-nano design I designed myself:


In both cases I tried to pick injections & pickup points at a bulk decoupling site that has many vias to both ground and the power plane with the injection point close to the power supply. Also note that the eval board uses 0201 sized parts where my own design uses 0402 parts. When converting the S21 attenuation to impedance, both designs are well within specs.


--- Quote ---Is it a good idea to follow the dev board schematic? No if the PDN on your own board is different.

--- End quote ---
Yes and no. In the end the power connections on the package and the layout guidelines (like placing the DDR memory within a few mm of the SoC, layer use, stackup, etc) limit the possible routing strategies (assuming a capable PCB designer). Or put differently: if you follow the layout guidelines where it comes to component placement, layer use and stackup you are not likely to screw things up. OTOH, if you just get creative with the schematic, you are on your own.

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