How Fast Could Serial Bits, Read from a Table in SRAM, Be outputted?

[NorthGuy]

Perhaps, someday, I will have the chance to order such MCUs; assuming I will be allowed to download the assembler of this advanced family.
I have C51 assembler for the ATMEL old MCUs.

Do you have PIC16 or PIC18 MCUs? They're even older than AVR and should be available anywhere in the world. They have better command sets, so you should be able to do it with 2-instruction cycles. Or you can hard-code bits into the code which will give you 1-instruction cycles. 139 hard-coded sequences 100-command each will take 14k commands, which will easily fit in a relatively big PIC18.

[KerimF]

Do you have PIC16 or PIC18 MCUs? They're even older than AVR and should be available anywhere in the world. They have better command sets, so you should be able to do it with 2-instruction cycles. Or you can hard-code bits into the code which will give you 1-instruction cycles. 139 hard-coded sequences 100-command each will take 14k commands, which will easily fit in a relatively big PIC18.

Just to be sure that I understood you well, do you mean by using PIC instructions, it is possible to output serial bits (read from a table in loop) at a rate of 2-cycle or even 1-cycle per bit? Thank you.

I ask this just by curiosity. You kindly suggest me to use PIC MCUs. But since many decades ago, I don't have the privilege to download the PIC assembler (MPLAB?).

[westfw]

using PIC instructions, it is possible to output serial bits ... at a rate of 2-cycle or even 1-cycle per bit?

Don't forget that on the 8bit PICs, "1 cycle" is 4 clocks.  Many of them run at 64MHz max speed, so that turns out similar to a 16MHz AVR, but still...

[westfw]

Quote

Recently I came across a trick that apparently helps with smoothing PWM output a lot while adding minimal hardware.

As some of EDN's "Design Ideas"?
https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction-revisited/
https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction-but-no-inverter/
https://www.edn.com/double-up-on-and-ease-the-filtering-requirements-for-pwms/

[KerimF]

As some of EDN's "Design Ideas"?
https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction-revisited/
https://www.edn.com/cancel-pwm-dac-ripple-with-analog-subtraction-but-no-inverter/
https://www.edn.com/double-up-on-and-ease-the-filtering-requirements-for-pwms/

I am afraid that, as I mentioned earlier, these techniques seem not to work when the application (like of a sinewave generator) needs to generate frequencies in a relatively wide bandwidth; for example, from 20 KHz down to 650 Hz. But perhaps I am wrong.

For instance, I try using DSS (Delta Sinewave Synthesis) instead of DDS (Digital Direct Synthesis) to simplify the hardware by using the old AVR MCUs, I have (like ATmega8 or ATmega32), which can output 4-cycle per bit (delta clock= 2,000,000 Hz, 8 MHz crystal). In this case, one conventional active low pass filter only (3-degree type, for example) would be needed at the MCU output pin for all frequencies from 20 KHz to 650 Hz (no need for precise values for the circuit resistors and capacitors).

[NorthGuy]

Just to be sure that I understood you well, do you mean by using PIC instructions, it is possible to output serial bits (read from a table in loop) at a rate of 2-cycle or even 1-cycle per bit? Thank you.

Yes, one instruction (called BTFSC) tests the bit in RAM and depending on the result executes or skips the next instruction. The second instruction (called BTG) flips the output pin. You encode your data in RAM so that there's 1 where you need to flip the bit, or 0 where you need to keep the bit the same. You need to make room for looping, so you need to reserve some fixed place in your sine curve where the output doesn't change for few instruction times (that is at the peak of the sine wave) and use it to insert looping instructions which would jump back to the appropriate place depending on the duration of the sequence being generated. You would need to align each sine wave in RAM so that the position of the "jumping place" in all your waves is always the same.

1-instruction cycle is possible with any CPU, as long as you have an instruction allowing you to set the output to high and another instruction allowing you to set the output to low. You also need fixed instruction time of course. Then, when you need to create a sequence which lasts, say, 108 instruction cycles, you just write a sequence of 108 instructions which produce the sequence.

Then you look at what you've done and observe that some of the instructions will not change the output. Such instructions may be replaced with nops, or with other instructions to organize looping or to do other useful things.

If you need 139 different sequences, you only need enough ROM to place them all in, which is not that much. If you need thousands of different frequencies or the range of frequencies is wide, this would be no-go. However, you can generate additional frequencies by altering the CPU clock.

I ask this just by curiosity. You kindly suggest me to use PIC MCUs. But since many decades ago, I don't have the privilege to download the PIC assembler (MPLAB?).

You can download them from the Microchip web site. VPN should allow you downloading no matter where you are. They have archives of old software going many years back. You need older ones where they have MPASM assembler.

[voltsandjolts]

OK; being in Syria you probably can't get modern chips

I'm sure ali-express would still ship to Syria, along with other Chinese entities.
Surely that would negate the need for this thread?

[Doctorandus_P]

I am afraid that, as I mentioned earlier, these techniques seem not to work when the application (like of a sinewave generator) needs to generate frequencies in a relatively wide bandwidth; for example, from 20 KHz down to 650 Hz. But perhaps I am wrong.

A lot of the PWM filtering techniques are designed around the goal of creating an DC voltage with a very small to no ripple, and they do not help much if you want to make varying signals such as approximating a sine wave. Although that "cancel-pwm-dac-ripple-with-analog-subtraction-revisited" promises to be quite good with varying signal output too.

One method that always works of course is to use faster PWM, but you would need other hardware for that. microcontrollers that run at a few hundred MHz are no exception, and some have extra high resolution timers that can push the PWM frequency another few orders of magnitude higher.

If you want to stick with your AVR hardware, then upping it's frequency to the maximum helps. If you go from 8MHz to 16MHz, you double the PWM frequency, can also double the cutoff frequency of your RC filter, and that halves the ripple.

If you want to use some pulse shaping, pulse density, or dither technique, then abusing on of the peripherals is the most logical choice, and and SPI port is the most logical for an AVR. That way, you can let the peripheral shift out bits while the microcontroller is either fetching the next byte from a buffer or calculating the next set of 8 bits.

But if you want performance, the AVR's were quite nice microcontrollers 20 years ago, but there is so much much better (faster) stuff around, that trying to squeeze the last few percent of performance out of an AVR is not very practical. You can do it just for fun, or as a brain teaser how far you can push it, but if it's for the performance to cost ratio, or look at the hours it takes to get that extra bit of performance, then it's a waste of time.

[KerimF]

Yes, one instruction (called BTFSC) tests the bit in RAM and depending on the result executes or skips the next instruction. The second instruction (called BTG) flips the output pin...

Thank you for your detailed description.

You can download them from the Microchip web site. VPN should allow you downloading no matter where you are. They have archives of old software going many years back. You need older ones where they have MPASM assembler.

Microchip apologizes for not having the right to do so (to open any of their doors for me).
On the other hand, I used to enter from front doors always. And, since MPASM (or the like) is a propriety of Microchip and Microchip shouldn't provide any service to me, entering now any of their back doors is out of question to me. This may sound somehow silly, but this is how I am.

Salut,
Kerim

[voltsandjolts]

OK; being in Syria you probably can't get modern chips

I'm sure ali-express would still ship to Syria, along with other Chinese entities.
Surely that would negate the need for this thread?

I wish what you say could be true in reality now. But this was true in the golden years, before year 2011 (before the world's decided to also save the people among whom I was born and live). Now, small private businesses, as mine, are no more allowed to transfer any amount of money to order the goods they need for work, as electronic components (but, naturally, the bosses in the high class still have this privilege).

After all, you are right. In fact, if I was born where you are I would also see this topic as being somehow non-sense.

OK, so Chinese entities will still ship to Syria, but ability to pay them is the problem.
Genuine question:
What prevents you from paying, while the higher classes can do so? Is it your own government's rules (perhaps based on ethnicity?) or something else?
I understand if you prefer not to answer.
Thanks.

[voltsandjolts]

Well, you lost me there. Good luck with the arb gen.

[rstofer]

I would pull the SRAM address generation outside the uC with a synchronous reset parallel loadable binary counter to generate the address.  There would be an additional column to carry the counter reset signal which is true when the address is at the end of the pattern.  The clock would cause the counter to increment and when the reset signal went true, the next address would be reset to zero.

I would need some logic to allow the uC to reach the SRAM to set up the table but once initialized, no uC intervention required other than to generate the clock for the counter.  Even that could be pulled outside with one of the clock divider chips. (internal PLL, dividers, etc).

Zero overhead, one clock per bit.

[KerimF]

I would pull the SRAM address generation outside the uC with a synchronous reset parallel loadable binary counter to generate the address.  There would be an additional column to carry the counter reset signal which is true when the address is at the end of the pattern.  The clock would cause the counter to increment and when the reset signal went true, the next address would be reset to zero.

I would need some logic to allow the uC to reach the SRAM to set up the table but once initialized, no uC intervention required other than to generate the clock for the counter.  Even that could be pulled outside with one of the clock divider chips. (internal PLL, dividers, etc).

Zero overhead, one clock per bit.

Good solution, thank you.

It follows somehow the general rule:
Using more hardware helps getting better performance in some respects.
(much like, having more memory space helps writing faster code).

[PCB.Wiz]

Recently I came across a trick that apparently helps with smoothing PWM output a lot while adding minimal hardware.

The Idea is that you make an inverted copy  of the PWM signal, and then use a second RC combination, but with the resistor and capacitor in series, and then add that to the output of the original RC filter.

The Idea is that the AC part of the two "shark fin" signals cancel each other out, while maintaining the DC output, because the inverted channels is AC coupled. When you do this, you have to modify the RC time constant to fit your new circuit.

EDN has done two versions of this. The step response is faster than a second order filter, and the stop band is similar, but the stop band does rely on the null effect (ie component matching)
* Addit: I see this link is already given in #28 )

https://www.ednasia.com/cancel-pwm-dac-ripple-with-analog-subtraction-revisited/

[PCB.Wiz]

I am afraid that, as I mentioned earlier, these techniques seem not to work when the application (like of a sinewave generator) needs to generate frequencies in a relatively wide bandwidth; for example, from 20 KHz down to 650 Hz. But perhaps I am wrong.

They filter the PWM content frequency, the filtered output frequency has different constraints.

At 20kHz your limit is the finite number of samples per full cycle.
At 650Hz you get 30x as many X axis samples, but the step filtering in the Y axis may be limited by encoding or RAM sizes.