how to indent VHDL and VERILOG sources ? (looking for an app/tool)

[legacy]

hi guys
i need to "indent" a lot of VHDL and VERILOG code,
just in order to make it look prettier
are there any tools to do that ?

i can use both Windows/Linux

[nctnico]

There are code beautyfier tools which apply a certain formatting to a source file. Google 'code beautyfier'.

[legacy]

i found C/C++ beautifier, are you sure there is a VHDL/VERILOG ones, too ?
if so, any suggestion about the specific one i'd better use ?

[jahonen]

Emacs VHDL mode has a beautifier at least for VHDL.

Regards,
Janne

[legacy]

umm, if it is possible i'd prefer something i can use in script (bash or windows), i have a tone of .vhd files to be beautified

[FrankBuss]

umm, if it is possible i'd prefer something i can use in script (bash or windows), i have a tone of .vhd files to be beautified

I'm sure for the experts it would be just 3 lines of Emacs Lisp code

[legacy]

i do not know anything about lisp and emacs but .. i can learn it 

[zapta]

Some ide's and editors can operate on entire directory trees, try eclipse, sublime, textpad, etc.

Sent from my Nexus 5 using Tapatalk

[scientist]

The Mojo IDE automatically formats VHDL, http://embeddedmicro.com/tutorials/mojo/mojo-ide although it's only in alpha.

[maxslug]

If you're prettying it up just to browse you might consider using http://www.burbleland.com/v2html/v2html.html to make your life easier.

-m