Electronics > Microcontrollers

how to indent VHDL and VERILOG sources ? (looking for an app/tool)

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legacy:
hi guys
i need to "indent" a lot of VHDL and VERILOG code,
just in order to make it look prettier
are there any tools to do that ?

i can use both Windows/Linux

nctnico:
There are code beautyfier tools which apply a certain formatting to a source file. Google 'code beautyfier'.

legacy:
i found C/C++ beautifier, are you sure there is a VHDL/VERILOG ones, too ?
if so, any suggestion about the specific one i'd better use ?

jahonen:
Emacs VHDL mode has a beautifier at least for VHDL.

Regards,
Janne

legacy:
umm, if it is possible i'd prefer something i can use in script (bash or windows), i have a tone of .vhd files to be beautified

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