How to JTAG a Ti DM368

[bozmanx105]

Im looking for some advice on how to JTAG a TI TMS320DM368.

I have a Jlink and have tried with both Jlink commander and OpenOCD.

I have decided to settle on using OpenOCD for now so that I am focusing on just one application and not continually changing what is required.

basically, I get the all zeros error when I attempt to connect.

It doesnt matter what device I load in OpenOCD it still fails (dm365, Ice, DaVinci).

I have gone back and read the TI document again and also obtained the BSDL file. Im not sure how to incorporate this into OpenOCD. There is also a note in the BSDL file that states

"The chip RESET will need to be high before trying to do boundary scan. If the BSDL tool does not use TRST pin, please put a 10K Ohm pull up resistor on this pin."

I assume the BDSL tool is OpenOCD and that I should add a pull up resistor to the TRST/Reset pin on the JTAG on the board? I have tried this but it fails to make any difference.

If anyone has had experience with the TI TMS320DM368 and OpenOCD I would be really appreciative of some help to get this running. I believe that this combination of software and hardware should be able to work together. TI doesnt support this CPU any more and Stegger dont provide any support for it either with there software. All of the relevant articles appear to no longer exist on the old TI WIKI but I was able to get a copy from Github. Even then the information is vague at best and has holes in it.

Hoping someone can provide advice or a good push in the right direction. 

The goal is to be able to flash the NAND but I cant currently see anything via the JLINK and OpenOCD.

There are lots of videos on using JLINK commander and OpenOCD but the info on waring tends to be very generic. I have a 10 pin JTAG connector on the board and I am making the assumption it follows the 10 pin standard.

[abyrvalg]

Most likely you are using OpenOCD in debug mode, not boundary scan. There should be two more pins (in addition to JTAG TCK, TDI, ...): EMU0, EMU1, try grounding them both - this should configure JTAG port for direct ARM core access. In default state JTAG port exposes a SoC-specific ICEPick TAP router module and perhaps OpenOCD doesn't know how to control it on this SoC.

Also, this SoC has many "external" boot modes like UART or USB. No loader tools for those modes?

[slugrustle]

The BSDL file is primarily going to be useful for JTAG Boundary Scan (IEEE 1149.1), which is all about reading and writing I/O pins for board level testing.  The BSDL file might talk about the debug TAP (Test Access Port), or a second file might talk about the debug TAP; that could be useful for programming, but the boundary scan TAP won't be.

abyrvalg's advice sounds good.

[bozmanx105]

Thanks for the extra info, I have been trying to get some sense out of the extra pins that are talked about. My JTAG only has 10 pin so these pins might not be exposed. There are other boot options but we are yet to find the pins that change the boot. I have had the chip taken off one board and we are about to start tracking where the boot select goes.

[rsjsouza]

Apart from what was already said (the BSDL will not help you), the DM368 has an ARM9 core. In this case, there is a very high probability that you will need Adaptive Clocking - an extra clock pin named RTCK. 

https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_adaptive_clocking.html

That said, from a JTAG perspective the DM368 is very similar (if not identical) to its more popular cousins DM355 and DM365. These other two devices are featured in the OpenOCD sources.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/8218/updated-dm355-cfg-for-openocd
https://github.com/openocd-org/openocd/blob/master/tcl/target/ti_dm365.cfg

Good luck!

[abyrvalg]

Adaptive clocking isn’t critical, its purpose is to synchronize TCK with system clock when TCK frequency gets close to system clock frequency. With slow TCK everything works w/o RTCK.

[rsjsouza]

In my experience with its sister ARM9-based devices (DM355, DM6446, OMAPL137, OMAPL138), the TCK has to be put lower than 1MHz for the non-adaptive connection to succeed. Also, when the core PLL is programmed for full speed (OMAPL devices is what I recall, but the other DaVinci devices weren't that different), the connection was cut off.

[bozmanx105]

I dont know if the em1 and em0 pins are exposed anywhere. I recently had the chip removed from a board to see if I could find it the boot pins were exposed somewhere but so far no luck. It seems odd that they would not be. Clearly the manufacture has a process at time of build and that they would have created some way to reflash the boot just in case it failed.  So far I am at a loss of where to go to from here. I have been working on this project for about 8 months.

[rsjsouza]

If you are wasting so much time with this, can you ditch OpenOCD for now and download Code Composer Studio to validate the hardware connections? It supports Jlink and, IIRC, DM368 (or any sister device that is identical from a JTAG standpoint, such as the DM365)

[bozmanx105]

Thanks for the suggestion, I do have code composer so it might be worth switching. There are a few variables, Im trying not to change too many of them but this is one worth doing.