How to read a txt file into VHDL ROM?

[matrixofdynamism]

I am designing a processor which shall store instructions in a ROM (as expected).

For purpose of simulation I want to parse a text file and load the contents of the result into a huge std_logic_vector into the ROM. The actual file shall store instructions in an assembly like format, they shall have to parsed and translated into binary words for std_logic_vector.

How do I do this? This should happen as soon as the simulation starts.

[Bassman59]

I am designing a processor which shall store instructions in a ROM (as expected).

For purpose of simulation I want to parse a text file and load the contents of the result into a huge std_logic_vector into the ROM. The actual file shall store instructions in an assembly like format, they shall have to parsed and translated into binary words for std_logic_vector.

How do I do this? This should happen as soon as the simulation starts.

Look into the VHDL textio library; it's a standard thing.

[hamster_nz]

See page 241of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/xst_v6s6.pdf

Specifying RAM Initial Contents in an External Data File
• Use the file read function in the HDL source code to load the RAM initial contents
from an external data file.
– The external data file is an ASCII text file with any name.
– Each line in the external data file describes the initial content at an address
position in the RAM.
– There must be as many lines in the external data file as there are rows in the
RAM array. An insufficient number of lines is flagged.
– The addressable position related to a given line is defined by the direction of
the primary range of the signal modeling the RAM.
– You can represent RAM content in either binary or hexadecimal. You cannot
mix both.
– The external data file cannot contain any other content, such as comments.