i am looking for an easy vhdl RISC SoC

[legacy]

hi guys
i have looked at open cores org but i haven't find nothing that matches with my constraints
- easy ( i do not have resources/time to look at big project, also i am not so skilled about HDL)
- written in vhdl code (i do not have any tool for verilog, systemC, etc)
- full SoC, CPU plus {RAM, UART, TIMER}
- toolchain supported (i need to program it in C)
- RISC oriented (with/without pipeline implementation)

could you suggest me something ?

[hamster_nz]

Have a look at the zpuino project.

http://www.alvie.com/zpuino/

[legacy]

already seen, but

1) it is not RISC, it is stack machine
2) it is too much big with a lot of things arranged into a complex tree
3) it is board oriented, especially for Xilinx Spartan3e, which means the bram has been planned and arranged into b24 format, which is not portable and which requires Xilinx tools in order to load an elf inside the bram
4) i not like the project at all

i am looking for something simpler and smaller, MIPS_I for example

[miguelvp]

OpenRisc 1000 at open cores, but it's verilog

Soft core from ARM but unless you are a student it's probably cost prohibited but I have not inquire to the cost so it's an unknown (cortex-m0 through m3 I think).Not sure if in VHDL or Verilog
There are some dev kits for under $1000 I think around $600 and not sure what kind of license they supply
Google Cortex-M0 soft core

There is an ARM core on open cores but it's in beta and not sure of what it has.

or get an SoC FPGA based dev kit like this one for $200
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836

If you are going to require a RISC processor why not get an FPGA that already has it built in?

[free_electron]

- easy ( i do not have resources/time to look at big project, also i am not so skilled about HDL)

depends on your definition of easy. an SOC is a very complex device. a core is a simple device . flick an 8051 in there.

- written in vhdl code (i do not have any tool for verilog, systemC, etc)

whaddayamean i don't have tools ? synopsys , modelsim , quartus, ISE all are language agnostic. it doesn't matter if using VHDL or Verilog.

- full SoC, CPU plus {RAM, UART, TIMER}

that's not a Soc (not according to my definition. it only starts being an soc once it has DMA , MMU , FPU , MAC, SATA, USB, and a crapload of other stuff on board.. .. grab a 8051 core. has ram ,uarts, timers, gpio. all you want. it is a pure harvard machine. easy to work with. well known core, tons of tools and compilers.

- toolchain supported (i need to program it in C)

8051 works fine. plenty of c compilers for it

- RISC oriented (with/without pipeline implementation)

oregano systems has a pipelined 8051 core. as for RISC. why do you want half arsed processors with only 5 instructions where you have to do all the work. the more instructions the better.


This smells like homework. "Must be risc, Must be VHDL , Must be C, MUST be pipelined" , because these are the requirements of the course... not because the application demands these features.

[legacy]

depends on your definition of easy. an SOC is a very complex device. a core is a simple device . flick an 8051 in there.

easy means
- no cache
- no MMU
- no DMA
- no strange features that increase the complexity of the whole

whaddayamean i don't have tools ? synopsys , modelsim , quartus, ISE all are language agnostic. it doesn't matter if using VHDL or Verilog.

because
- i have "VHDL studio" (it is a tool, simulator), it accepts only VHDL
- my Tina license for HDL accepts only VHDL (i have not enough money to buy the Verilog license)
- i both VHDL design book, i do not have any Verilog Book
- i know VHDL, i am learning Verilog

that's not a Soc (not according to my definition

SoC stands for System On Chip, a minimal System is composed by
- CPU
- RAM/ROM (where it boots and executes application (.text), and where it load/store data (.data))
- something to interact with it, usually a serial port (uart plus RS232 of FTI-uart-to-usb)

that is minimal SoC, than you can add
- DMA
- FPU
- MMU
- LAN
- SATA
- USB
- LCD (like HD44780
- LCD LVDS (like the laptop one)
- GPIO
- a crapload of other stuff on board

8051 works fine. plenty of c compilers for it

8051
- It is not RISC, it is CISC
- it may be pipelined
- it may be fast (like Dallas 80C400, or more faster)
- it is not a Von Neumann machine, data and code are leaving on separated spaces (except than if you mix PSEN with rd/wr, i don't know if it is still possible when the flash is inside the Chip)
- It is supported by SDCC, gcc and llvm are not able to compile for it.
- Also it is 8bit, i'd like pure 32bit machine.

why do you want half arsed processors with only 5 instructions where you have to do all the work. the more instructions the better

a MIPS32 core may be fantastic: a lot of instructions and possibilities (i think)

This smells like homework. "Must be risc, Must be VHDL , Must be C, MUST be pipelined" , because these are the requirements of the course... not because the application demands these features.

because i want it that way, it's for hobby learning purpose, i know MIPS very well (i know ARM for the most, i worked with nxp LPC2888 realizing an arm prototype board), but the greatest part of what i have read, studied and understood has the contents of a lot of MIPS skills (the book "See the MIPS run", for example, or the experience with the "MIPS INC Atlas board") and now for my hobby i have limited amount of time.

I mean i could learn 8051 and toy with it on fpga (if i found a good 8051-SoC in VHDL), but i do not know 8051 in details, i have toyed with Dallas Tini-Java (which is 80C390, '51 core), but it was 2001 and i have no tools and skills for it.

[hamster_nz]

This smells like homework. "Must be risc, Must be VHDL , Must be C, MUST be pipelined" , because these are the requirements of the course... not because the application demands these features.

I guess the original poster believes that writing a complete pipelined RISC core, creating periherals, verifying it and building C toolchain support is a trivial task, it should take no more than a handful of VHDL files. On top of that it doesn't need to leverage any of underlying FPGA features to work efficiently.

If I was to rephrase his requirements in software terms he might see how unrealistic they are:

I want a small cross-platfrom OS, requirements are:
- easy ( i do not have resources/time to look at big project, also i am not so skilled about C)
- written in C code
- full networking stack, SCSI I/O stack and GUI
- hardware independant - must work on any CPU
- Should be POSIX complient, and RTOS would be nice
- Performance equivilent to Linux

I've had a look at Linux, but it doesn't support my target CPU, and the codebase is too large.

[legacy]

OpenRisc 1000 at open cores, but it's verilog

I have seen it, it's too much complex for me =P
I have Spartan3e-500 board, with only 500Kgates
the OR1K is a bit big for such  an FPGA


I have seen System09, that is 6809 + uart + timer + VDU
that's not so complex, it fits well on my spartan3e
it also has a gcc port, but … it is CISC 8bit 

[legacy]

I want a small cross-platfrom OS, requirements are:
- easy ( i do not have resources/time to look at big project, also i am not so skilled about C)

I am skilled about C and asm (m68k, mips, arm)
but i have no resources/time to look at big projects
i am trying to plan activities for my free time, and i have fixed slots of free time
something like 10 hours/week,
plus sometimes an extra during weekend

- written in C code

yes, i know C, i do not know ADA
but i know pascal
and i wrote a bare board interpreter which looks like pascal
obviously it's a toy, an homework, but it's fun

- full networking stack, SCSI I/O stack and GUI

not interested about this, i have put ucOS/2 on an LXP ARM node
that's for a job task, it has taken me a lot of time, but i had fun
(also, the most important things, i was payed for it) so it's fine "that's all folks"

- hardware independant - must work on any CPU

well, a bit of C code may be ported from/to my other projects
i hope the 20% at least

- Should be POSIX compliant

not required

and RTOS would be nice

RTOS ? nahh, i already had fun with ucos/2 and VxWorks at job
(writing drivers and helping other to fix things)

i do not want to see any RTOS in my hobby free time

- Performance equivilent to Linux

i got a Raspberry for it, i do not need anything else, and i do not want to put linux to anything else
my laptop has already gentoo on, i am already fine with linux

I've had a look at Linux, but it doesn't support my target CPU, and the codebase is too large.

 

[miguelvp]

Just leaving this here since you didn't reply about the arm soft core:
http://www.arm.com/support/university/ip/index.php

A student's report using this:
http://web.fi.uba.ar/~pmartos/publicaciones/SPL2011_Cortex-M0ImplementationOnAXilinxFPGA.pdf
ARMs version of that paper (about the same but not sure which one is the final version)
http://www.arm.com/files/pdf/SASE2011_ImplementingTheCortexM0DesignStartProcessorInALowEndFPGA.pdf

Still your best bet would be one of those combined FPGA/SoC chips that at least Altera is producing (as linked on my previous post), not sure about Xilinx.

[legacy]

yes, ARM is RISC, it is 32bit machine, it is great for my purpose !
i have only Xilinx chip/devboards,  so i will look for FPGA/SoC knocking at Xilinx's doors

great, thank you for the ARM link!

[joelby]

Andrew Zonenberg has written a MIPS-1 compatible core: https://code.google.com/p/utica-softcore/ . He's also working on an updated version (apparently not yet released to the public) that can be targeted with mips-linux-gnu GCC - perhaps this one can too? Verilog, though.

[Rory]

I'm surprised no-one has mentioned the Cypress PSoC. 

[nctnico]

If you are using a Xilinx FPGA you can use ISE which has support for Verilog. I'm currently working on a project which uses the Lattice Mico32 core which is written in Verilog.

[legacy]

I'm surprised no-one has mentioned the Cypress PSoC.

tell me more

[legacy]

Andrew Zonenberg has written a MIPS-1 compatible core

amazing, i have written a bit of MIPS-1 code (40% in assembly) so it could be fun 

[legacy]

Lattice Mico32 core which is written in Verilog.

Never used it, i am curious. Have you got a minimal working SoC ?

About Verilog, yes, ISE can handled it, but … my Tina HDL license is for VHDL only
i am used to study HDL with TINA HDL plus VHDL Studio

consider that i am skilled about C/Asm but i am a quite new about HDL
and that's my hobby's purpose: something to aim for, having fun 

[Codemonkey]

Why restrict yourself to whatever Tina can support ? Why not just use for example Quartus from Altera and use the free copy of Modelsim that they provide ? You can use whatever language you want then.

[Rory]

I'm surprised no-one has mentioned the Cypress PSoC.

tell me more

This is what I'm playing with right now:
Cypress PSoC 5LP series: http://www.cypress.com/psoc5lp/

[nctnico]

Lattice Mico32 core which is written in Verilog.

Never used it, i am curious. Have you got a minimal working SoC ?

Yes. I have UART, SPI, I2C and GPIO. But there are many more modules available. It is steep climb though fully understand how to connect everything using the Wishbone bus using crossbars.

[legacy]

Yes. I have UART, SPI, I2C and GPIO. But there are many more modules available. It is steep climb though fully understand how to connect everything using the Wishbone bus using crossbars.

yeah, the crossbar instead of the classical bus (used in ASIC CPU system), very amazing idea!]

which project, in particular, are you talking about ? I mean any public repo available ?

[nctnico]

The project I have been working on is based on this open source project from CERN:
http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core

[legacy]

very very nice, i like it a lot, thank you for the link =)