rp2040 MCU pll derived clocks jitter?

[iMo]

Hi, did by chance an experienced enthusiast here ever measured the jitter of the clocks created by its pll?
For example the original pico board or clones like waveshare's pico-zero etc?
Thanks.

[nctnico]

Not for this MCU particulary but expect quite a bit of jitter as many of these PLLs seems to be actually DPLLs which use chained delay elements instead of a VCO.

[dobsonr741]

@iMo how did you come to the conclusion the clock jitters?

[iMo]

@iMo how did you come to the conclusion the clock jitters?

I did not come to the conclusion the clock jitters, I've been asking here on some measurement data availability, if any.

[Kleinstein]

@iMo how did you come to the conclusion the clock jitters?

There is not question that there is jitter on the clock. There is always some jitter, the question is only how much. Jitter or phase noise is not so simple to describe, as one often has more than simple white phase noise.

I am afraid there could be quite a lot of jitter, as the RP2040 modules have a switched mode regulator and thus likely some ripple on the supply, that will translate to FM modulation of the clock.
The other point is that the chip is more made for low power than a super stable clock.

There is a project for a frequency counter (AFAIR also a version with extra time interpolator) build around the RP2040 - this may give some hints.

[SiliconWizard]

I have no real figure for this, but I have a few Pico boards around and am familiar with the RP2040, so I guess I could try evaluating it - be aware that it may (probably does) depend on the PLL parameters, and that if I do this, I will most probably not spend time testing all possible multiplication factors. But I can try that in the typical 125 MHz core clock setting, outputting a derived clock on one GPIO (using PWM probably) and estimate the jitter. I'll follow up if/when I get around to doing this. Unless someone else beats me to it.

[iMo]

I have a pico-zero here (linear voltage regulator), 3 crappy scopes, I doubt any of them is suitable for for such a measurement. That would require a timenut like equipment, my bet.

[Kleinstein]

It did some search and found a possibly relevant page:
https://forums.raspberrypi.com/viewtopic.php?t=366021

This is a report of more than just normal jitter, but some odd extra delay.

For testing one could do a somewhat similar test: build 2 channels of simple PWM DAC  (e.g. 74AC04 or similar as buffers and some RC filtering) that output a 50/50 signal with a different phase. The difference of the 2 output signals should show the relevant error due to jitter.

The other way would be someone with a reasonable good spectrum analyser to look at an attenuated square wave signal.

[iMo]

I saw that "bug report" couple days back, read it several times, but frankly, I do not understand fully what the guy did with his multimeter measuring "voltages of his pwm signals".. (he is not writing there he made 2 "PWM DACs" measuring the voltage there)..

PS: when you set a fractional division somewhere (some config routines declare the divider "float" in order to set the fractional div), you may get large jitter, of course..

I've been generating pwm 16us period 50% duty sig on a pin, but watching the scope shows perfect stable edges/period, no way to see a jitter that way..

..
#include "hardware/pwm.h"

int main() {
    set_sys_clock_khz(96000, true);  // set 96MHz CPU0 clock for example
    stdio_init_all();

    // Experimental PWM clock output  period 16usecs 50% duty
    uint PINpwm = 0;                                                       // use pico's PIN 0 as the PWM output
   gpio_set_function(PINpwm, GPIO_FUNC_PWM);
   
   uint osc_slice = pwm_gpio_to_slice_num(PINpwm);
   pwm_set_clkdiv_int_frac(osc_slice, 96, 0);               //pwm clock 96MHz/96=1MHz
   pwm_set_wrap(osc_slice, 16-1);                             // 16 periods in a pwm cycle
    pwm_set_enabled(osc_slice, true);
   pwm_set_chan_level(osc_slice, pwm_gpio_to_channel(PINpwm), 8 );  //set 50% duty
..

[iMo]

When measuring the jitter, the jitter value should depend on the pll setting.
The datasheet says you get the minimal jitter when setting the pll's vco frequency close to the max 1596MHz, with the dividers set such you get the CPU clock.

The setting of a specific CPU clock could be done with different settings, thus the jitter differences should be visible.

There is a python script for calculation of the vco_freq frequency and the 2 pll dividers:

https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_clocks/scripts/vcocalc.py

and you may set the CPU clock freq based on that numbers

set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2)

with the vco_freq in Hz.

For example:

Code: [Select]

C:\Users\JohnSmith\Desktop>python vcocalc.py 96
Requested: 96.0 MHz
Achieved: 96.0 MHz
REFDIV: 1
FBDIV: 128 (VCO = 1536.0 MHz)
PD1: 4
PD2: 4

set_sys_clock_pll(1536000000L, 4, 4);

[nctnico]

My expectation is that the jitter will be ballpark between 100ps to 200ps peak-peak.

[PCB.Wiz]

When measuring the jitter, the jitter value should depend on the pll setting.
The datasheet says you get the minimal jitter when setting the pll's vco frequency close to the max 1596MHz, with the dividers set such you get the CPU clock.

Yes, and note it will also depend on what else the Pico is doing.

Being an active digital device, the ground /supply noise will affect the oscillator.

For lowest jitter, I've seen a (different micro) PCB changed to external clock, as they found digital pins near the XIN pin, had a measurable degrade effect on PLL.

Of course, low noise power supply also helps.

A quick search found a couple of reports of people feeding CMOS oscillators into XIN

I have a pico-zero here (linear voltage regulator), 3 crappy scopes, I doubt any of them is suitable for for such a measurement. That would require a timenut like equipment, my bet.

A simple XOR gate and low pass filter into a audio sound card could  give you some idea of close-in jitter.
If you use an external low jitter oscillator, that can feed one side of the XOR, then various PLL settings can compare on the the pin.

[SiliconWizard]

The question of whether it matters should also be considered. If you need a low-jitter clock, you can feed an external clock to the RP2040. Note that the datasheet specs a Fmax of 50 MHz. But the clocking scheme is flexible, so you could use the internal PLL as a clock source for the core and an external clock for some peripherals (as long as 50 MHz max. is ok.)

[iMo]

Yep, that has been mentioned in the other thread (DYI Multislope ADC) as well, where the Pico is used as the inguard MCU. The jitter has been identified as a potential source of errors (talking 6+ digits), therefore my interest on getting some numbers on the jitter provided somebody has measured that already..