I keep my own Cliffs Notes references on stuff like this, to get me back up to speed on stuff I don't use everyday. i2c is one of those things. Most of this is condensed from the typical online references, but organized into something easily digestible. This is device-agnostic, but maybe it will help clear things up?
Synopsis:
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I2C uses a bi-directional bus topology, using two wires: Serial Clock (SCL), and Serial Data (SDA).
Devices are individually addressed and communicate via a master/slave relationship. Any device can claim mastership by taking control of the clock and initiating communication. Slaves only communicate in response to a query by the master.
Communication is usually between a master and a single slave, though it is possible to initiate a broadcast, called a General Call, by writing to a special address (0x00).
SMBus is a subset of I2C. Vendors may use other names to avoid trademark infringement, such as Two-Wire Interface (TWI).
Electrical:
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Every device is connected to the SCL and SDA bus via an open drain interface. The bus voltage is not defined, but is often 3.3v or 5v. The bus idles high via a pull-up resistor, and is pulled LOW by a device to transmit. In this way, devices with differing supply voltages can communicate, provided they are tolerant of the bus idle voltage. This can be accomplished through the use of clamping diodes or active level converters.
The bus must have a total capacitance of 400pF or less to retain the transition edges at higher speeds, otherwise active termination may be necessary.
Bus:
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All nodes on the SCL and SDA lines are connected in parallel, along with a pull-up resistor to Vbus. Devices become high-impedance when they are not transmitting.
Data rate is determined by the serial clock, which is generated by the master, and runs only while devices are actively transmitting data. The actual clock speed is abitrary - the master can pulse the clock at any frequency up to its maximum, determined by the following speed classes:
10kHz Low Speed Mode [Ls]
100kHz Standard Mode
400kHz Fast Mode [Fm]
1.0MHz Fast Mode Plus [Fm+]
3.4MHz High-Speed Mode [Hs]
5.0MHz Ultra Fast Mode [UFm] (requires active pull-up)
These modes determine the maximum speed at which a device can (or is configured to) communicate. Devices do not negotiate their capabilities, so the designer must ensure all devices are limited to the slowest on the bus.
In practice, the actual maximum throughput will be reduced to some degree by interaction of the devices on the bus, and the electrical characteristics of the bus itself.
During the clock's LOW phase, any device can hold SCL LOW as a method of flow-control. This is called clock stretching, and is commonly used when a device needs to prepare its data buffer, process data, or prepare a response. The transmitting device must monitor SCL after releasing it, and wait until the line floats high before proceeding.
The actual rise time will be affected by the electrical properties of the bus -- that is, the pull-up resistor's value; the inductance of wires, leads, and traces; and the total bus capacitance.
On the data bus, a binary zero is represented by logic LOW, and binary one is represented by logic HIGH. A bit is written by pulling the clock line LOW, holding SDA as required (either pulling it LOW, or letting it float HIGH), waiting for the bit to propagate, then allowing SCL to float HIGH. As other devices notice SCL is HIGH, they will read the bit on SDA. After a suitable period of time, the transmitting device can pull SCL LOW again and write the next bit.
A reasonable hold time for 100kHz bus speeds is 4uS. (Each cycle takes at least 10uS at this speed.)
If two (or more) devices attemp to claim the bus at the same time, the SCL pulses will appear to be stretched by the slower of the two devices. This does not inherently indicate a fault to any device on the bus. The transmitting device(s) must also monitor the SDA line in a process called arbitration. Since the SDA line idles HIGH, a transmitting device will only detect a collision when it attempts to signal a binary one (SDA HIGH), but reads back a zero (SDA LOW) instead. Upon detecting this condition, the transmitting device should yield and wait for the bus to become idle again. This carries on until one device wins by nature of sending the first unique binary zero.
It is theorhetically possible for multiple devices to simultaneously transmit identical messages unbeknownst to each other, but if this happens, the net effect is still a successful transmission.
Addressing:
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Devices functioning in a slave capacity are programmed to respond to an unique address. If the master device will never operate as a slave, its address is optional. Slave devices respond in a transactional model -- that is, the recipient of the slave's transmission is implied -- so only the master's initial query is directed to an address. The slave's response immediately follows the initial query, still clocked by the master. The slave will hold the SCL line LOW, if necessary, to provide time for internal processing.
Addresses are either 7-bit (most common) or 10-bit.
In I2C, slave devices are often simple components with very little intelligence. Their address is sometimes fixed, or partially fixed with programmable least-significant digit(s). This can limit the number of similar devices that can coexist on a single bus, and may even cause conflicts between different devices that happen to respond to the same address.
Protocol:
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I2C defines only a minimal transaction framework. Each device will build upon this simple process with higher level protocols to provide whatever functionality it is meant to offer. Everything above the basic transport mechanism is application-specific.
In a typical I2C implementation, the master device will be a microcontroller, and slave devices will be single-purpose components, such as temperature sensors, fan speed monitors, or ADC/DACs. With simple devices the command structure will be minimal -- perhaps only returning or accepting a raw data value in response to a read or write query.
Devices with some minimal state awareness, such as EEPROM chips or user interface controllers, may require bidirectional commands to first request a data address (memory location, button, or indicator), and then write to, or read from, that address.
More complex implementations may devise a packet-oriented "multi-master" scheme, where a device writes a message to another device, ends the I2C transaction, then waits asychronously for any further reply. In this case, devices may participate in both master and slave roles.
In an I2C transaction, an active device can be in one of four modes:
Master Transmit - The device initiated the transaction and is sending data to a slave
Master Receive - The device initiated the transaction and is receiving data from a slave
Slave Transmit - The device is sending data to the master
Slave Receive - The device is receiving data from the master
To begin a transaction, the master device will send a START bit, the target device's address, then a READ/WRITE flag bit to define the intended operation. The slave sends an acknowledgement (ACK) bit if it is present and able to communicate, then the transfer occurs as indicated by the read/write flag.
If the master wishes to write data, it will proceed to do so, waiting for an ACK bit after each byte. In a read operation, the master retains control of the clock while the slave writes to SDA, with the master sending an ACK bit after each byte.
To abort a transfer, the receiving device can send a NACK bit at the end of a cycle. The master may then send a STOP bit to release the bus.
Frame Format:
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All data is sent in MSB (most-significant bit first) order.
While the bus is idle, both SCL and SDA will be HIGH. To start a transaction, the master device will pull SDA LOW to indicate a START bit, then pull SCL LOW. The master will then send the target address and READ/WRITE bit. Each data bit is written to SDA while SCL is LOW, and read by all devices while SCL is HIGH.
v Data sampled here
_____|__ | ____________
SDA | \______|_<____________>...
_____|______ | ______
SCL | \__|____/ \___...
| |
IDLE | START | ^ Data written here
Binary zero is indicated by pulling SDA LOW, and one by letting it float HIGH. The READ/WRITE flag is READ when SDA is HIGH (1), or WRITE when SDA is LOW (0).
After writing the final bit to SDA, the master will release and read SCL. If any other devices are stretching the clock, SCL will remain LOW until they acquiesce, and then SCL will return HIGH again. (This is the 'read' portion of the final bit's cycle.)
The master will then pull SCL LOW again and release SDA -- this is the start of the ACK cycle. The slave device is then expected to acknowledge the data by pulling SDA LOW. After waiting one typical clock cycle, the master will release SCL and examine SDA for the ACK bit.
v SDA set by master v SDA set by slave
_____|__ | | _________ | | __________|_
SDA | \______|____________|_/ ...\__________|_/ | \__________...
_____|______ | _____ | _____ | _____ | _____ | _____
SCL | \__|___/ \__|___/ \_...__/ \__|___/ \__|___/ \__...
| | | | | |
IDLE | START | Addr6 == 0 | Addr5 == 1 | Addr0 == 0 | READ Mode | ACK
An ACK bit is asserted when SDA is LOW, or NACK when SDA is HIGH. In this manner, if a device does not respond to the given address, the idle bus will intrinsically signify NACK.
If the query was acknowledged, the transaction continues. If the master wishes to write, it will begin sending one byte of data, followed by another clock pulse during which the slave should provide an ACK bit. Further bytes will be sent in this manner until the master completes its transfer, or receieves a NACK reply.
In a read operation (after sending address and READ bits), the master watches for ACK. Once received, the slave will begin transferring data. The master continues generating the clock, but the slave can stretch each cycle as necessary. The master must generate an ACK after every byte. If the master is no longer interested in receiving more data, it can generate a NACK to end the transfer.
At the end of a transaction, the master is required to release the bus with a STOP bit. It does this by pulling SDA LOW, releasing SCL, then releasing SDA. To begin a new transmission, the master can issue a RESTART condition. In this case, the master holds SDA HIGH, releases SCL (HIGH), then pulls SDA LOW again.
_____|__ __|____ ____|__ _______
SDA | \______ ... ______/ | ... | \______ ... _/ \______...
_____|______ ______|____ ____|______ _______
SCL | \__ ... __/ | ... | \__ ... _____/ \__...
| | |
IDLE | START STOP | IDLE | START RESTART
The only time SDA is changed during a HIGH clock period is during a START, STOP, or RESTART condition. This is useful to determine when the bus needs attention. When SDA falls while SCL is high, a device has claimed mastership and will be sending an address byte. This can be used in an interrupt service routine, or as a hardware trigger, to wake a device from sleep mode and/or begin monitoring for traffic. Once the address is transmitted, the receiver can decide whether any further action is necessary until the next START/RESTART condition.
If a device is waiting with queued data, it can watch for a rising SDA on SCL HIGH. This indicates the bus is returning to an idle state and is ready for a new transaction.
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