I2S DMA not running on SAME51 when TXCTRL.bit.DMA = 1

[Chicopy]

Hi,
I have troubles with ATSAME51 I2S (not) running DMA transfers.
I was able to configure I2S & DMA to transmit data to stereo Codec corectly when was TXCTRL.bit.DMA = 0;
i.e. single DMA channel is used to transmit data of both audio channels, organized  samp[1]_Left, samp[1]_Right, samp[2]_Left, samp[2]_Right,...

Problem starts since I wanted to set TXCTRL.bit.DMA = 1;  // DMA=1: even-numbered and odd-numbered slots use separate DMA channels
I have configured
DMA channel[0] to make 256 transfers of data from Left-audio-channel-buffer to I2S->TXDATA.reg, and
DMA channel[1] to make 256 transfers of data from Right-audio-channel-buffer to I2S->TXDATA.reg.

According to datasheet DS60001507E / page 1900,  51.6.8.1 DMA Operation,  there must be used 2 triggers for Transmitter,
one for "even" and second for "odd" slot.

// Table 51-3. I2C DMA Request Generation
//   SERCTRLm.DMA     Mode         Slot Parity     DMA Request Trigger
//   -------------------------------------------------------------------
//             0      Receiver     all             I2S_DMAC_ID_RX_m
//                    Transmitter  all             I2S_DMAC_ID_TX_m
//   -------------------------------------------------------------------  we have SERCTRLm.DMA=1
//             1      Receiver     even            I2S_DMAC_ID_RX_m
//                                      odd             I2S_DMAC_ID_TX_m
//                    Transmitter  even            I2S_DMAC_ID_TX_m       <0x4E=> I2S Tx 0 Trigger
//                                      odd             I2S_DMAC_ID_RX_m       <0x4C=> I2S Rx 0 Trigger
//   -------------------------------------------------------------------

I used DMA channel[0] with trigger <0x4E=> I2S Tx 0 Trigger, and channel[1] with trigger <0x4C=> I2S Rx 0 Trigger.
As it didn't make any transfers (constantly 0000... on SDO line) I also tried to swap them, and also many other combinations of triggers:
// <0x4C=> I2S Rx 0 Trigger
// <0x4D=> I2S Rx 1 Trigger
// <0x4E=> I2S Tx 0 Trigger
// <0x4F=> I2S Tx 1 Trigger

Is there anybody who managed to use 2 separate DMA channels, each for one slot (audio-channel) ?
(i.e. that uses TXCTRL.bit.DMA = 1)

Example of source code that works would help me a lot.

Mainly would help me to know:
- which 2 triggers are supposed to be used
- whether both TXCTRL.bit.DMA = 1;  and also RXCTRL.bit.DMA = 1; must be set
- whether also RX-Serializer must be enabled (because is needed trigger I2S_DMAC_ID_RX_m)
- whether for RX-Serializer must be used Clock Unit 1

I think I have already spent few weeks on it and tried everything (all 4 lines above, all combinations of triggers), but nothing works.
Thanks for any tips or code.

[ataradov]

I have not used and have not seen anyone use DMA=1. It is possible that there is some hardware issue or configuration trickery.

I don't even know how it is supposed to work. Those requests make no sense unless in separate channel mode you can only do RX or TX, but not both.

In any case, I would double check if it is DMA is not being triggered or something goes wrong after that. Does DMA generate any transfer complete interrupts? Any changes to the programmed counts?

[Chicopy]

I am actually porting to E51 my older project that successfully used DMA=1 from D21.
On D21 the DMA=1 thing worked as described in datasheet;
Only TX-serializer was enabled, 2 DMA channels used, channel[0] sending data for Left-channel, and channel[1] sending 0 to Right-channel (not used).

Now on the E51 I am watching I2S bus with logic analyzer, for DMA channel[0] is enabled interrupt TCMPL,
interrupt handler contains counter of "transfer complete" interrupts (still 0, even after 1s running).
Transmissions are (not) started via
I2S->CTRLA.reg = 0x3E;  // RXEN=1, TXEN=1, CKEN1=1, CKEN0=1, ENABLE=1

i.e. both serializers should be running;
1s after start I print most of I2S and DMA registers and wb_descriptors:

DMA diff 1s = 0           // this is the counter of DMA channel[0] "transfer complete"

I2S Registers:
CTRLA     3E
CLKCTRL0  030F4087
CLKCTRL1  030F4087
INTENSET  0000
INTFLAG   2211
SYNCBUSY  0000
TXCTRL   02FC0080
RXCTRL   00FC00A0
TXDATA    00000000
RXDATA    00000000

DMA Registers:
CTRL      0F02
CRCCTRL   0000
CRCDATAIN 00000000
CRCCHKSUM 00000000
CRCSTATUS 00
DBGCTRL   00
SWTRIGCTRL 00000000
PRICTRL0  40404040
INTPEND   0000
INTSTATUS 00000000
BUSYCH    00000000
PENDCH    00000000
ACTIVE    00FD0100
BASEADDR  200000F0
WRBADDR   200002F0

• .CHCTRLA   00204C02
[0].CHCTRLB   00

• .CHPRILVL  00
[0].CHEVCTRL  00

• .CHINTENCLR  02
[0].CHINTENSET  02

• .CHINTFLAG   00
[0].CHSTATUS    00
[1].CHCTRLA   00204E02
[1].CHCTRLB   00
[1].CHPRILVL  00
[1].CHEVCTRL  00
[1].CHINTENCLR  00
[1].CHINTENSET  00
[1].CHINTFLAG   00
[1].CHSTATUS    00
wb_descriptor[0] BTCTRL_1609 BTCNT_0100
SRCADDR_20002344 DSTADDR_43002830 DESCADDR_200004F0
wb_descriptor[1] BTCTRL_1201 BTCNT_0100
SRCADDR_20000524 DSTADDR_43002830 DESCADDR_20000100

I found that if a 10x reading of I2S->RXDATA.reg (+delays 10ms) is added after the 1s testing, then it generates transmissions of 10 words from buffer.
Now I think that might be necessary to configure & enable 2 more DMA channels to read from I2S->RXDATA.reg ,
using the same triggers like 2 existing DMA channels that make writes to I2S->TXDATA.reg .
I.e. maybe is not possible to do only transmissions to stereo Codec without runnig also dummy reception side. I will try.

[Chicopy]

talking to myself, hoping somebody could join..

attached is code (not very clean, sorry) that uses bit DMA=1, only in TXCTRL, not in RXCTRL;
used are 4 DMA channels, {0} and [1] for TX side, [2] and [3] for RX side.

The channels [2][3] have to run, despite I didn't want to implement reading from Codec;
but it seems to have to run, probably because trigger  <0x4C=> I2S Rx 0 Trigger  is needed.

Currently the DMA transfers are running and content of one buffer is transmitted to odd slot, and content of second buffer is transmitted to even slot.
Unfortunately it doesn't run correctly.
- data from DMA channel [1] are correct  (data in buffer are 32b, some flags in 16 MSBs + counter in 16 LSBs, samples are incremented +1, correct)
- data from DMA channel {0} are NOT correct  (samples are incremented +2 !)
- I don't check channels [2][3], am not interested on RX side yet

DMA channels {0} and [1] are configured the same way, no idea why {0} skips every second sample while [1] runs correctly:
...
descriptor[0].BTCTRL.bit.BLOCKACT = 0x1;   // No action at last block, channel disable + block interrupt
descriptor[0].BTCTRL.bit.BEATSIZE = 0x2;   // 2 = 32-bit bus transfer, needed for I2S !
descriptor[0].BTCTRL.bit.SRCINC   = 0x1;   // Source increment is enabled
descriptor[0].BTCTRL.bit.DSTINC   = 0x0;   // Destination increment disabled
descriptor[0].BTCTRL.bit.STEPSEL  = 0x1;   // Step applies to Source
descriptor[0].BTCTRL.bit.STEPSIZE = 0x0;   // Step size is X1

Any tips ?