Input PWM Duty Cycle limiting

[zer0c00l]

I have input PWM signal with arbitrary frequency and duty cycle, and I have to limit the duty cycle of the output PWM to a set value. If the input PWM duty cycle is lower than that set duty cycle than it can pass, if it is higher, than the output PWM duty cycle gets limited to the set duty cycle. So far I have been successful in creating a duty cycle limiter module that works by measuring the input PWM high pulse length and low pulse length, and calculating the duty cycle based on that, but this module doesn't work if the input pwm signal duty cycle varies continuously. It will work if the input duty cycle changes but than stays constant after that. How can I make it work if the duty cycle keeps changing and I am unable to measure the pulse widths. Input PWM frequency can go up to 100Khz, whereas the FPGA is using a clock of 50MHz.

[hamster_nz]

If the duty PWM frequency changes very rapidly then I don't think you can make this work, as your design can't see into the future. It also depends on how the PWM pulse is aligned (rising edge vs falling edge vs symmetrical)

Unless you define exactly what the input is and how you want the system will behave you will always end up with what looks like a buggy output when there is a discontinuous change in the input PWM signal.

[zer0c00l]

If the duty PWM frequency changes very rapidly then I don't think you can make this work, as your design can't see into the future.

That is exactly what I noticed while I was working on the current implementation. I just wanted to make sure I wasn't missing anything that could make this work

[langwadt]

if you don't know the period you can't predict what is too much or too little, and if you delay every thing a cycle you run out of time at increasing frequency

[zer0c00l]

if you don't know the period you can't predict what is too much or too little, and if you delay every thing a cycle you run out of time at increasing frequency

Talking about delaying everything, I did have this idea of implementing some kind of pipeline where the signal gets measured in the first stages and then that information can be used in the later stages to limit the duty cycle. Would something like this work (it does seems it would in my head). Please correct me if I am wrong

[langwadt]

if you don't know the period you can't predict what is too much or too little, and if you delay every thing a cycle you run out of time at increasing frequency

Talking about delaying everything, I did have this idea of implementing some kind of pipeline where the signal gets measured in the first stages and then that information can be used in the later stages to limit the duty cycle. Would something like this work (it does seems it would in my head). Please correct me if I am wrong

when the period gets shorter you don't have enough time to run the previous cycle

[zer0c00l]

when the period gets shorter you don't have enough time to run the previous cycle

But if the clock (50Mhz) is considerably faster than the PWM frequency (max 100Khz), shouldn't that help

[hamster_nz]

when the period gets shorter you don't have enough time to run the previous cycle

But if the clock (50Mhz) is considerably faster than the PWM frequency (max 100Khz), shouldn't that help

Imagine your PWM limit is 50%

If you sketch a transition from a 20% 100kHz signal to a 20% 1kHz PWM signal (and you will need a lot of paper...) the problem will become apparent.

How soon can you know for sure that it is now a 1kHZ/20%, vs being a 100% 100kHz (which needs to be limited)  or a 2% 100Hz signal (which doesn't)?

Actually, as soon as you get a 0% or 100% input signal the entire thing degenerates to a mess, as you have nothing of the PWM frequency left in the input signal!

[aheid]

It's not clear to me if the PWM frequency will change or not. Is it fixed, just unknown or will it change while the PWM signal is active?

If it changes I wonder what the point of this limiting is.

[NorthGuy]

As it stands now, it' unsolvable.

Say, you get your signal constantly high. This may be interpreted as 100% duty cycle at 1MHz, or as a begging of a positive pulse with very low duty cycle at 1pHz. There's absolutely no way to tell.

You need to tell why you are limiting the duty cycle, whether your goal allows to constraint the frequency band, what amounts of frequency distortions you can tolerate, what lag can you tolerate etc. Once you have a defined purpose, you can start working on the solution.

[SiliconWizard]

As said above, it isn't solvable in the general case.

Now depending on the characteristics of the input PWM signal (is the frequency arbitrary, but fixed over a large number of PWM cycles, is there a defined min an max frequency you can rely on, for instance) and your expectations, you may be able to work something out.

I'm thinking of something as the following: if it's acceptable not to be cycle-accurate, you could implement a PWM frequency and duty cycle estimator based on a few input PWM cycles in a moving average manner, and set your output signal with those parameters (limiting the duty cycle would then just be a matter of limiting the estimated input duty cycle). Of course it would degrade the frequency response, delay and resolution, but it may be acceptable depending on your requirements. To handle the 100% duty cycle case, you could have a state machine that would use a default output frequency until your frequency estimator settles (that is, until it has seen a few PWM cycles with transitions to low level, thus a duty cycle < 100%, allowing it to determine both the period and duty cycle). The other case, considering your frequency estimator has settled and then there are pulses with 100% duty cyle (that you would detect if the input signal is high for longer than the max PWM period you defined (min frequency), would either reset your state machine (thus resetting the frequency estimator to a default value), or the frequency estimator would use the last estimated frequency until it can estimate a new one.

Obviously as said above that has limitations so you'd have to determine whether those are acceptable.

[zer0c00l]

when the period gets shorter you don't have enough time to run the previous cycle

But if the clock (50Mhz) is considerably faster than the PWM frequency (max 100Khz), shouldn't that help

Imagine your PWM limit is 50%

If you sketch a transition from a 20% 100kHz signal to a 20% 1kHz PWM signal (and you will need a lot of paper...) the problem will become apparent.

How soon can you know for sure that it is now a 1kHZ/20%, vs being a 100% 100kHz (which needs to be limited)  or a 2% 100Hz signal (which doesn't)?

Actually, as soon as you get a 0% or 100% input signal the entire thing degenerates to a mess, as you have nothing of the PWM frequency left in the input signal!

Thanks for the explanation. It makes sense

As it stands now, it' unsolvable.

Say, you get your signal constantly high. This may be interpreted as 100% duty cycle at 1MHz, or as a begging of a positive pulse with very low duty cycle at 1pHz. There's absolutely no way to tell.

You need to tell why you are limiting the duty cycle, whether your goal allows to constraint the frequency band, what amounts of frequency distortions you can tolerate, what lag can you tolerate etc. Once you have a defined purpose, you can start working on the solution.

This limiter module sits between a variable PWM generator and a device (sort of like a motor) that operates using the PWM pulses. The idea is to be able to limit the PWM pulse that is getting to the device to a particular duty cycle using this limiter module. I won't have control over the PWM generator itself so I came up with this idea of a limiter module.

As said above, it isn't solvable in the general case.

Now depending on the characteristics of the input PWM signal (is the frequency arbitrary, but fixed over a large number of PWM cycles, is there a defined min an max frequency you can rely on, for instance) and your expectations, you may be able to work something out.

I'm thinking of something as the following: if it's acceptable not to be cycle-accurate, you could implement a PWM frequency and duty cycle estimator based on a few input PWM cycles in a moving average manner, and set your output signal with those parameters (limiting the duty cycle would then just be a matter of limiting the estimated input duty cycle). Of course it would degrade the frequency response, delay and resolution, but it may be acceptable depending on your requirements. To handle the 100% duty cycle case, you could have a state machine that would use a default output frequency until your frequency estimator settles (that is, until it has seen a few PWM cycles with transitions to low level, thus a duty cycle < 100%, allowing it to determine both the period and duty cycle). The other case, considering your frequency estimator has settled and then there are pulses with 100% duty cyle (that you would detect if the input signal is high for longer than the max PWM period you defined (min frequency), would either reset your state machine (thus resetting the frequency estimator to a default value), or the frequency estimator would use the last estimated frequency until it can estimate a new one.

Obviously as said above that has limitations so you'd have to determine whether those are acceptable.

That seems like a good idea

[Buriedcode]

If the frequency is fixed, and reasonable latency (as in say, 10 PWM periods which could be massive or tiny depending on the application) the simplest way I can think of would be converting the PWM to a voltage, limiting that, then using it to create a new PWM signal of similar frequency.  Phase and frequency will of course be different, but it could be done in all analogue, and the "limit" would be easily adjustable by a voltage on a comparator.

At 100kHz, doing this digitally would be tough, and as stated not workable without some restrictions - namely fixed frequency, and non-phase correct PWM..  100kHz = 10us period.  1% = 100ns shortest pulse.  Getting something to work over a *range* of frequencies is harder still.  Still doable on a sufficiently fast platform, possibly even FPGA as you mentioned, but there will always be latency between the change in input PWM duty, and output duty.  I think you will have to narrow down what kind of latency is acceptable.   Is this PWM part of a control loop?  If it's just open loop control, then it might not be much of a problem.

[NorthGuy]

You're likely to get a constant frequency. So, measure the frequency for some period of time. Then calculate the pulse width which corresponds to your maximum allowable duty cycle. Then chop all the pulses which are longer than your calculated width. You can do it with nearly no lag.

Adjust your frequency measurements (and consequently the pulse width estimates) slowly if needed.