I was able to retrieve an initial version of the assembly code that I did in the past to self-test the instructions but it isn't complete. I still want to share it just to give an idea about what I'm talking about.
.text
.global test_opcodes
test_opcodes:
; Registers back up
PUSH {R0, R1}
; MOV, CMP and B opcodes
MOV R0, #0xB2
CMP R0, #0xB2
BNE fault_exit
; ADD opcode
ADD R0, R0, #0x13
CMP R0, #0xC5
BNE fault_exit
; SUB opcode
SUB R0, R0, #0xB1
CMP R0, #0x14
BNE fault_exit
; Registers roll back
POP {R0, R1}
; Return
MOV PC, LR
Regarding the open source RISC-V verification IP path, it sounds like an interesting idea but I'm still not familiar with RISC-V architecture and therefore can't evaluate the effort. It seems to me quite different and challenging in terms of adaptation to the equivalent ARM instruction set.
In an effort to maintain granularity in coding of instruction tests by using assembly language, I discovered a tool called Godbolt:
https://godbolt.org/. It converts C code into assembly, making it particularly helpful for those less familiar with assembly. If the generated assembly code doesn't include the specific instruction you're looking to test, you can enforce it by including #include <arm_acle.h> and using the corresponding C instruction-functions from the library. For example, the function __sadd16(a, b) translates directly into the SADD16 instruction in the assembly output on Godbolt.