STM8S103 trigger standard mode, reset mode , gated mode , request help

[Sajeev]

Dear Forum members,
I am trying to test the trigger standard mode , trigger reset mode and gated trigger mode on stm8S103 TSSOP20 version. I initialized the registers as described in RM0016 manual . The Timer1 counter keeps on counting on its own and doesnt wait for the trigger to happen on TI1 or TI2 inputs (PC6 & PC7). The AFRO0 option byte was enabled to make timer1 chanel 1 and chanel 2 available. Request help form informed members on how to realise the trigger modes. Please find below the code I used. I have used the TIMER1 _ chanel2 as input and timer1 overflow interrupt to toggle an led on PD4. The led is supposed to toggle when the PC7 goes high but I see the LED toggles when power is applied to the chip even when PC7 is supplied ground.
Regards
Sajeev


main_loop.l
   mov CLK_CKDIVR,#$00   ; cpu clock no divisor = 16mhz
   bset PD_DDR,#4      ; set PD4 as output
   bset PD_CR1,#4      ; set PD4 as pushpull
timer_setup
   bres TIM1_CR1,#0   ; disable timer
   bres TIM1_SR1,#0   ; clear update interrupt flag
   mov TIM1_SMCR,#$66  ; TS = 110 and SMS = 110 , TI2 input , trigger standard mode
   bset TIM1_IER,#0   ; enable update interrupt
   bset TIM1_CR1,#0   ; enable timer
   RIM
   
wait
   jra wait
   
   
   
   interrupt TIM1_ISR
TIM1_ISR
   bres TIM1_SR1,#0 ; clear interrupt flag
   bcpl PD_ODR,#4   ;toggle led pin
   iret

[rhodges]

It looks like you want to use "Trigger Gated Mode". Did you read that part of 17.4.5 and figure 51? The text says to set SMS=101 (and TS=101 for T1).

Go to 17.7.3 for the TIM1_SMCR register.

101: Trigger gated mode - The counter clock is enabled when the trigger signal (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.

110: Trigger standard mode - The counter starts at a rising edge of the trigger TRGI (but, it is not reset). Only the start of the counter is controlled.

[Sajeev]

Dear Sir,
Thankyou for the reply. The above code is actually for testing trigger standard mode. The registers are furnished based on the steps provided in the RM0016 manual section 17.4.5 page 155/467. Unfortunately I couldn't make it work. On connecting logic analyzer on PD4 it shows a 50% duty
with 4ms width without triggering TI2. I was expecting no toggling on PD4 till a high edge is detected on PC7 (TI2). Am i not doing it right?
Regards
Sajeev


Trigger standard mode
The counter can start in response to an event on a selected input.
Procedure
Use the following procedure to start the up-counter in response, for example, to a rising
edge on the TI2 input:
1.Configure channel 2 to detect rising edges on TI2. As no filter is required in this example, configure an input filter duration of 0 (IC2F = 0000). The capture prescaler is not used for triggering and does not need to be configured. The CC2S bits select the input capture source and do not need to be configured either. Write CC2P = 0 in the TIM1_CCER1 register to select rising edge polarity.
2. Configure the timer in trigger mode by writing SMS = 110 in the TIM1_SMCR register. Select TI2 as the input source by writing TS = 110 in the TIM1_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual reset of the counter is due to the
resynchronization circuit on TI2 input.

[rhodges]

C6 and C7 are pins for channels 1 and 2, not clock triggers. The only clock trigger I see is B3.

[Sajeev]

Dear Sir,
Thanks for the reply. Finally I got it working. I didnt follow the example in the RM0016 properly, thats why it didnt work. In the example ,its not mentioned to enable the timer1 by writing 0 bit of TIM1_CR1. I was enabling the timer1 in my code and it started counting directly without the need of a trigger on TI2. I removed that line and found that the PD4 doesnt toggle on power up. It starts toggling only when 5v is applied to TI2 (PC7). It seems that CEN bit of TIM1_CR1 need to set only in reset-trigger mode and gated-trigger mode. Please find below the corrected version of the code I used. Thanks once again for the advice.
Thanks & Regards
Sajeev




main_loop.l
   mov CLK_CKDIVR,#$00   ; cpu clock no divisor = 16mhz
gpio_setup:   
   bset PD_DDR,#4      ; set PD4 as output
   bset PD_CR1,#4      ; set PD4 as pushpull
   ;bset PC_CR1,#7      ; enable input and pull up, uncomment if falling edge needed
timer_setup:
   bres TIM1_CR1,#0   ; disable timer
   bres TIM1_SR1,#6   ; clear trigger interrupt flag
   mov TIM1_SMCR,#$66  ; TS = 110 and SMS = 110 , TI2 input , trigger standard mode
   ;bset TIM1_CCER1,#5  ; TI2 polarity falling edge , uncomment if falling edge needed
   bset TIM1_IER,#0   ; enable update interrupt
   bset TIM1_IER,#6   ; enable trigger interrupt
   RIM
   
wait:
   jp wait

   
   interrupt TIM1_ISR
TIM1_ISR
   bres TIM1_SR1,#0 ; clear interrupt flag
   bres TIM1_SR1,#6 ; clear interrupt flag
   bcpl PD_ODR,#4    ; each update interrupt at 4.09ms after counting 65535
   iret



   interrupt NonHandledInterrupt
NonHandledInterrupt.l
   iret

   segment 'vectit'
   dc.l {$82000000+main}                           ; reset
   dc.l {$82000000+NonHandledInterrupt}   ; trap
   dc.l {$82000000+NonHandledInterrupt}   ; irq0
   dc.l {$82000000+NonHandledInterrupt}   ; irq1
   dc.l {$82000000+NonHandledInterrupt}   ; irq2
   dc.l {$82000000+NonHandledInterrupt}   ; irq3
   dc.l {$82000000+NonHandledInterrupt}   ; irq4
   dc.l {$82000000+NonHandledInterrupt}   ; irq5
   dc.l {$82000000+NonHandledInterrupt}   ; irq6
   dc.l {$82000000+NonHandledInterrupt}   ; irq7
   dc.l {$82000000+NonHandledInterrupt}   ; irq8
   dc.l {$82000000+NonHandledInterrupt}   ; irq9
   dc.l {$82000000+NonHandledInterrupt}   ; irq10
   dc.l {$82000000+TIM1_ISR}   ; irq11
   dc.l {$82000000+NonHandledInterrupt}   ; irq12
   dc.l {$82000000+NonHandledInterrupt}   ; irq13
   dc.l {$82000000+NonHandledInterrupt}   ; irq14
   dc.l {$82000000+NonHandledInterrupt}   ; irq15
   dc.l {$82000000+NonHandledInterrupt}   ; irq16
   dc.l {$82000000+NonHandledInterrupt}   ; irq17
   dc.l {$82000000+NonHandledInterrupt}   ; irq18
   dc.l {$82000000+NonHandledInterrupt}   ; irq19
   dc.l {$82000000+NonHandledInterrupt}   ; irq20
   dc.l {$82000000+NonHandledInterrupt}   ; irq21
   dc.l {$82000000+NonHandledInterrupt}   ; irq22
   dc.l {$82000000+NonHandledInterrupt}   ; irq23
   dc.l {$82000000+NonHandledInterrupt}   ; irq24
   dc.l {$82000000+NonHandledInterrupt}   ; irq25
   dc.l {$82000000+NonHandledInterrupt}   ; irq26
   dc.l {$82000000+NonHandledInterrupt}   ; irq27
   dc.l {$82000000+NonHandledInterrupt}   ; irq28
   dc.l {$82000000+NonHandledInterrupt}   ; irq29

   end