SPI pins protection in case of two masters

[Unixon]

If two MCUs accidentally decide to become SPI masters at the same time this may fry few pins and I don't like it.
Is there anything better than putting series resistance on CLK/CS lines?
It bothers me that high output resistance on CLK may become a problem for really fast clocks.

[langwadt]

or/and gates, depending idle state?

[ejeffrey]

A parallel RC can allow fast signals through while limiting the DC current.

How high speed are we talking?  For really high speed like 100+ MHz flash where signal integrity is that important you would normally have only a single device per port.  That significanly limits the chances for contention.

[Unixon]

or/and gates, depending idle state?

Put bilateral switches on SCK/MISO/MOSI and convert CS to open drain and open switches only if one CS is low impedance and other one is high?

I imagine following suggestions in order of descending probability:
1. Design the firmware and the system architecture properly and never get in a situation when any two endpoints don't know their roles definitely at any moment;
2. Just put these resistor arrays in series on both ends of the bus and be happy.
3. Use additional circuitry to signal role change and resolve conflicts or use a different interface (CAN etc.)
4. <coming up> 

[mikeselectricstuff]

If two MCUs accidentally decide to become SPI masters at the same time this may fry few pins

No it won't.
Two MCU pins fighting isn't going to fry anything.
If you're really paranoid, add 100R series resistors.

[Unixon]

How high speed are we talking?

Currently I have a range of 10-300MHz on my mind.

[loose-electron]

Another alternative is to configure all attached ports to a node as passive pullup (external R) and active pull down. If things get into a tug of war, the worse that can happen are false states but no fried GPIO. 

Getting the arbitration right would be my preference.

[langwadt]

How high speed are we talking?

Currently I have a range of 10-300MHz on my mind.

at hundreds of MHz you'll have lots of other more important considerations than the risk of contention

[Unixon]

at hundreds of MHz you'll have lots of other more important considerations than the risk of contention

Oh, this is so true :'( Impedance matching, reflections and the company... yeah, a whole game of monsters to defeat.
Come to think of it... if we basically calculate the area under the curve... even ideally synchronous clocks will have at most 50% of time in short pulses... and everything else will be even less...

[ejeffrey]

10 MHz to 300 MHz is a pretty big range!

At 10 MHz, some series resistance is no big deal.

At 300 MHz you are probably in the realm of point to point links with short tracks and no stubs.  Remember, standard SPI already has very bad timing for the MISO signal.  You should just design something that can avoid contention by design.  Although an appropriate value source termination resistor would be good for signal integrity, so you might as well do that.

[Unixon]

10 MHz to 300 MHz is a pretty big range!

This comes from the slowest (at nominal/reasonable clock rate) to fastest MCU in possession - AVRs are in 1x-10x range, STM32 are up to high 10x - low 100x, WCH RISC-V are at 100x tops, and the top dog now is Artery at 240/288 MHz. ARM Cortex-A in GHz range are hopefully out of the question