What would be difference between clock latency and propagation delay?

[tip.can19]

FPGA/ASIC - I believe the clock latency is the total time it takes from the clock source to an end point. PFA latency.png

Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA propagation.png

So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture?

Thanks
Tip

[hans]

The propagation delay creates clock skew or latency. Just like wiring will also create it. It delays the edge traveling from point A to B.

Clock skew is measured between 2 points in a circuit. You want to minimize clock skew such that any delay on the clock network is roughly the same, such that the clock will arrive at the flipflops at roughly the same time.
I guess you could then define clock latency as the clock skew between the clock source and a node in question.

[hamster_nz]

Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA propagation.png

Propagation delay is the time it takes for an output of a system to change in response to a change of inputs. Only really makes sense with purely async logi. (where no clock signal is involved).

For synchronous logic other parameters make more sense, like setup time, hold time and clock-to-output delays.

[NorthGuy]

Conceptually, "latency" is the same as "delay".

Also, both the clock distribution system (fig.1) and the inverter (fig.2) are asynchronous circuits. The fact that the clock is used to synchronize flip-flops does not make the clock itself synchronous. This is why it is important to equalize delays through the clock system (thereby minimizing skew). In contrast, flip-flops are synchronized by the clock, therefore there's no need to equalize delays through the combinatorial logic feeding the flip-flops - the combinatorial delays may vary wildly as long as the setup and hold requirements of the flip-flops are met.

"Latency" often refers to performance. Thus, you wouldn't refer to combinatorial delays as "latency" because the performance in RTL system is set by the clock. Even if your combinatorial logic settles extremely fast, you still need to wait for the clock to affect the receiving flip-flop. Therefore, in RTL systems, the latency is determined by the number of clock cycles between inputs and outputs. However, smaller combinatorial delays may let you run the clock faster, thus decreasing the overall latency.

[tip.can19]

Thanks guys for helping me with your inputs! 

Regards