Interfacing to the parallel bus output of an ADC (AD7771) with a microcontroller

[super7800]

Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/AD7771.pdf
Timing found on page 57/58

So i'm trying to interface a SAMD21G18A running an Arduino bootloader with the parallel interface of the AD7771A. There are 6 pins coming from the ADC, four are parallel data, a clock output, and a ready signal. Basically all the makings of a QSPI interface with ADC-as-master.

My first thought was interrupts (basically bit-banging the interface), but that is proving very unreliable. I am wondering how the "correct" way of doing this is? would it be using a QSPI interface? (ideally not as this is a custom board already sitting before me, and the SAMD21 doesn't support QSPI).

I can get the data directly from the SPI interface aswell but that is not ideal. Ideally the data is received as fast as possible (not in samples/s but in processor cycles) so the processor can tend to its main task. Is using a QSPI interface a way to achieve this, the only way, the correct way? alternatives?

[ataradov]

What is your MCLK/DCLK?

Without looking into the details of the SPI protocol, I would guess that hardware SPI would be faster than software bit-banging. Especially given that you can do SPI using DMA or interrupts, leaving time for other things to run.

[DavidAlfa]

Can it make dma transfers using a Timer?
If so, you could set up a PWM timer at 50% duty, inverted mode (Output low while active) acting as the master clock.
Then setup a second PWM channel in the same timer with no output, set at slighly larger duty cycle (ex. 55%) duty (So it triggers slightly after the first PWM rised, to let the new data signal stabilize), which trigger the DMA.

[ataradov]

This is way too complicated, just use DMA with a regular SPI mode.

[DavidAlfa]

Ah, it's much easier, the clock comes from the ADC!
Then use the external interrupt controller, generating an event that triggers dma transfer from the GPIO to a circular buffer

It's 32bit per sample (24+8) and SPI Fmax is 30MHz, so with it you can still get ~937KSps, close to the ADC limit.

[Miyuki]

I'm using it successfully with STM32 SAI peripheral, you need some model with two instances but they can be cascaded and it works seamlessly
I do not know if you need Atmel's processor or if they have this peripheral available, but on STM it is easy

[Kleinstein]

The ADC seems to support a normal SPI mode too. That is definitely easier on the µC side than trying some QSPI in software.

[Miyuki]

The ADC seems to support a normal SPI mode too. That is definitely easier on the µC side than trying some QSPI in software.

But it significantly limits the sample rate
It might be a problem for some projects

[DavidAlfa]

Define "significantly".
Max ADC sample rate is 8ch*128KSps = 1024KSps
Taking SPI limit from datasheet (30MHz), achievable rate is 937KSps.
If you slighly overclock SPI to 33MHz (10% faster) then it'll reach full bandwidth.

[ataradov]

Keep in mind that SAM D21 SPI will not work that fast. So again, the approach depends on the sample rate and the amount of data that need to be captured at once. Without hardware way to capture that, capturing full speed 4-bit stream in the firmware may be challenging too. And doing DMA tricks to capture GPIO values may work, but there may not be a point in going too fast, SRAM will just fill and CPU may not be able to handle the data.

[langwadt]

Keep in mind that SAM D21 SPI will not work that fast. So again, the approach depends on the sample rate and the amount of data that need to be captured at once. Without hardware way to capture that, capturing full speed 4-bit stream in the firmware may be challenging too. And doing DMA tricks to capture GPIO values may work, but there may not be a point in going too fast, SRAM will just fill and CPU may not be able to handle the data.

I've never used the samd21, but afaict from the datasheet it can run spi slave at 1xAPB bus speed, max 48Mhz

[ataradov]

I've never used the samd21, but afaict from the datasheet it can run spi slave at 1xAPB bus speed, max 48Mhz

No, it can't do that. Max clock setting is 24 MHz, but if you look in the electrical specs, pad bandwidth would limit it to 12-16 MHz. Pad bandwidth can be ignored in some cases, especially for hobby stuff, but the maximum clock is fixed.

[langwadt]

I've never used the samd21, but afaict from the datasheet it can run spi slave at 1xAPB bus speed, max 48Mhz

No, it can't do that. Max clock setting is 24 MHz, but if you look in the electrical specs, pad bandwidth would limit it to 12-16 MHz. Pad bandwidth can be ignored in some cases, especially for hobby stuff, but the maximum clock is fixed.

I'll take your word for it, but I don't see it in the datasheet, https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D21_DA1_Family_DataSheet_DS40001882F.pdf

table 37-7 and table 37-67

[ataradov]

table 37-7 and table 37-67

Those are maximum clock frequencies that can be supplied to the peripheral input, this does not say anything about the performance of a specific peripheral.

Table 25-2. "Baud Rate Equations" - f_baud = f_ref / (2*(BAUD+1)), where BAUD is the register setting. If you set 0, then you get f_baud = f_ref / 2 = 48/2 = 24 MHz.

And Table 37-67. "SPI Timing Characteristics and Requirements" shows SCK period of 84 ns, so maximum frequency is 1/84e-9 = ~12 MHz.

[langwadt]

table 37-7 and table 37-67

Those are maximum clock frequencies that can be supplied to the peripheral input, this does not say anything about the performance of a specific peripheral.

Table 25-2. "Baud Rate Equations" - f_baud = f_ref / (2*(BAUD+1)), where BAUD is the register setting. If you set 0, then you get f_baud = f_ref / 2 = 48/2 = 24 MHz.

And Table 37-67. "SPI Timing Characteristics and Requirements" shows SCK period of 84 ns, so maximum frequency is 1/84e-9 = ~12 MHz.

that's for master mode, wasn't there a way for the ADC to be master?

[ataradov]

that's for master mode, wasn't there a way for the ADC to be master?

Not in SPI mode.

But also, the same pad limitations apply to the slave mode. The table says that it can go up to APB clock, but in practice making it work reliably at that clock is going to be next to impossible.

[Miyuki]

If you want to read data from AD7771 by config SPI, there is only debug read and it can read a value just from a single channel, you need to set the desired channel and do a conversion and then read data. It will be very slow.
Output can be configured as SPI master, but it is synchronous with the sampling clock, and over the single line you are limited to 1/4 of the max sample rate. You need to increase oversample or discard data from other channels.

[ataradov]

Once again, it all boils down to OP's sample frequency and sample duration requirements. The optimal approach would vary quite a bit based on that. Cortex-M0+ is not the power house of signal processing, you you have to be ready for things to be slow, even if you capture at a fast rate.

[super7800]

The device doesn't do anything with the data. It will record it for 30seconds to at most 2 minutes, then stream to PC

STM32 is an option, but id hate to have to order another board, as these are "special" boards that require fairly expensive processes due to their very small size (via-in-pad etc.) I will be ordering a new board, as i messed up somewhere else on the PCB anyways thats non-fixable without a revision (DOH!)

The SPI bus is very much non-ideal solution, as there is another, more important DUT on a (separate) SPI interface, and I would get very poor ADC sample rate due to that. Perhaps a multi-mcu solution may be needed (add a dedicated MCU for ADC buffer) (hopefully, very hopefully, not though).

Ah, it's much easier, the clock comes from the ADC!
Then use the external interrupt controller, generating an event that triggers dma transfer from the GPIO to a circular buffer

It's 32bit per sample (24+8) and SPI Fmax is 30MHz, so with it you can still get ~937KSps, close to the ADC limit.

@DavidAlfa definitely something to look into. i was already trying to do something similar with interrupts, but not using DMA. Ill try that and see if it works. I am very much not well-versed in the more advanced MCU functions though. This seems to show some good examples https://github.com/manitou48/ZERO

[dietert1]

A powerful device to implement high bandwidth/non-standard IO interfaces is a zynq MCU with FPGA fabric. I have seen a zynq in our Rigol scope. It's already the second question of this kind i have seen in this forum today.

Recently i spent an hour or so on whether one can make a realtime emulator for a 2 MHz 65SC02 on a STM32L433. Basically at 80 Mhz it should be possible. So i configured the MCU with a PWM counter to output the 2 MHz clock. Then i used an interrupt to generate the 6502 Synq signal. Probably the highest interrupt rate i was ever using on any MCU. It worked well but then i remembered that i wanted to run a USB stack on my MCU and put this aside. Such projects involve some kind of FPGA. The MCU is the wrong tool.

Regards, Dieter

[ataradov]

The device doesn't do anything with the data. It will record it for 30seconds to at most 2 minutes, then stream to PC

This device has 32 Kb of SRAM. Where are you going to store 2 minutes, or even 30 seconds of data sampled at high rate?

and I would get very poor ADC sample rate due to that.

Why? Interrupt driven SPI takes almost no resources.

[ataradov]

A powerful device to implement high bandwidth/non-standard IO interfaces is a zynq MCU with FPGA fabric.

So, you are suggesting to move from a $5 MCU to $70 FPGA requiring BGA process to sample some low speed ADC?

[dietert1]

Using an FPGA does not imply high cost. Its flexibility may save a lot of trouble, like board revisions. Appearently the OP has a problem there, too. And as you wrote, it won't be a $5 MCU anyway, due to record size.
It seems to be difficult to do it on a MCU, i mean selecting a MCU with the proper peripheral. If i hear that somebody found a trick using two instances of an SAI peripheral, that's also nothing to recommend.
Implementing a peripheral by bit-banging isn't always possible. That's why we have this thread.

Regards, Dieter

[Miyuki]

SAI peripheral in STM32 looks to be designed in a way that allows paralleling to get a wider interface, so I won't call it a trick, just using the resources
And you can run on a single instance (two-bit wide) at half the sample rate
We did consider using a small FPGA to do protocol translation to something easier to manage.
But a single-chip solution is always easier to work with and there is no cheap mid-size Cortex M4 or M7 with a small FPGA of just a few hundred cells.

[langwadt]

SAI peripheral in STM32 looks to be designed in a way that allows paralleling to get a wider interface, so I won't call it a trick, just using the resources
And you can run on a single instance (two-bit wide) at half the sample rate
We did consider using a small FPGA to do protocol translation to something easier to manage.
But a single-chip solution is always easier to work with and there is no cheap mid-size Cortex M4 or M7 with a small FPGA of just a few hundred cells.

will and M3 do?  https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-4K/Nano-4K.html