Is it worth it to learn 8051 architecture now?

[nctnico]

No the LW instruction. See: http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html

[westfw]

Loading a register with a 32bit constant doesn't need to be atomic... (perhaps "shouldn't"?  Surely you're not going to write an ISR that messes with register contents?!)

[CatalinaWOW]

So much angst about an architecture.  There are only two.  Dartmouth and Harvard.  In many flavors.  Once you have learned one of each kind it isn't that difficult to pick up the next one.

Many of the answers here aren't responding to the question - is it worth learning 8051, they are argueing about what the best architecture is.  Which doesn't have a singular answer.  Depends on your application, your customer, your tools, your background and a few other things.  Anwers given above are generally correct - for part of the question.

Is it worth learning 8051?  I would say there are two things which might make the answer yes - at least for a basic skill level.  Becoming a guru requires even better reasons.  One, if you haven't used something of that class before it is good to expand your knowledge base.  Two, if you have some particular hardware reason (a freight car load of chips, an application with full code available, a repair or upgrade on a legacy system or any number of similar things.)

[legacy]

No the LW instruction

so you bypass the problem through the load/store unit
which actually does a load/store of 32bit one-shot
and stalls the whole pipeline until conclusion
yes, it works 

[legacy]

Surely you're not going to write an ISR that messes with register contents?!

here we go, e.g. a software debugger is called in kernel space, sometimes beyond an ISR,
and it needs to access the register (or the context) contents
and in this case address must be completed
therefore you must assure the load-affective-address has completed before being interrupted

-> good practice and good habit 

[westfw]

has anyone seen a "Classic 8051" (40pin 51, 2*28pin memory, etc) PCB around in "modern formats"? (Open source EAGLE PCB or something?)

Does anyone want to do a design/schematic/pcb review of such a board?
8051 + 32pin JEDEC device + FTDI connector + I2C serial EEPROM (maybe, for "serial download to EEPROM and bootloader into RAM.") 100x50mm for cheap fab...


 

[technix]

has anyone seen a "Classic 8051" (40pin 51, 2*28pin memory, etc) PCB around in "modern formats"? (Open source EAGLE PCB or something?)

Does anyone want to do a design/schematic/pcb review of such a board?
8051 + 32pin JEDEC device + FTDI connector + I2C serial EEPROM (maybe, for "serial download to EEPROM and bootloader into RAM.") 100x50mm for cheap fab...

I have cooked up a design:
* AT89C51RC @ 24MHz (any 8031 or 8032 would work though, but chips with flash allows the internal ROM being used as a boot loader)
* I-bus and D-bus fused on the board (so the XRAM and XROM are really the same bus, effectively a Princeton architecture)
* GAL16V8 as bus matrix controller, reads A15..11, RD, WR and PSEN, emits OE, WE and 6 chip selects
* 3x AT28C64 (or FM16W08) for 24kB NVRAM at 0x0000-0x5fff
* IS61C256 for 32kB SRAM at 0x8000-0xffff
* HD44780-compatible LCD at 0x7800-0x7fff (0x7800-7bff goes to IREG, 0x7c00-0x7fff goes to DREG
* External bus interface at 0x6000-0x77ff and one chip select
* Port 1 and port 3 broken out as-is, except UART pins
* ATtiny2313A @ 12MHz for USB to Serial adapter, 8051 POR and entering boot loader mode
* 100% through hole construction

[westfw]

* 3x AT28C64 (or FM16W08) for 24kB NVRAM at 0x0000-0x5fff
* IS61C256 for 32kB SRAM at 0x8000-0xffff

Sigh.  That's about what I figured.   Once you go to multiple chips, everybody has different ideas about what they want/need.
(as it happens, I have SO much 32pin EPROM, RAM, and NVRAM, I'm not really interested in anything that decodes for 8kbyte chips.)

[legacy]

has anyone seen a "Classic 8051" (40pin 51, 2*28pin memory, etc) PCB around in "modern formats"?
(Open source EAGLE PCB or something?)

sure 

[nctnico]

* 3x AT28C64 (or FM16W08) for 24kB NVRAM at 0x0000-0x5fff
* IS61C256 for 32kB SRAM at 0x8000-0xffff

Sigh.  That's about what I figured.   Once you go to multiple chips, everybody has different ideas about what they want/need.
(as it happens, I have SO much 32pin EPROM, RAM, and NVRAM, I'm not really interested in anything that decodes for 8kbyte chips.)

The posts about the boards do take me back a couple of decades. I designed several boards like that for various purposes and with different microcontrollers as well. Good old times -sigh-. Where is the man-with-grey-beard emoticon?

[technix]

* 3x AT28C64 (or FM16W08) for 24kB NVRAM at 0x0000-0x5fff
* IS61C256 for 32kB SRAM at 0x8000-0xffff

Sigh.  That's about what I figured.   Once you go to multiple chips, everybody has different ideas about what they want/need.
(as it happens, I have SO much 32pin EPROM, RAM, and NVRAM, I'm not really interested in anything that decodes for 8kbyte chips.)

I am running 8051 in Princeton architecture, with XRAM and XROM pointing to the same location. That is a major change in system architecture implemented on the board level. I gave it 24kB NVRAM (notice I am not calling it ROM here, instead it is called NVRAM) and 32kB SRAM so the programmer can have adequate code and data space, as you can put code into the NVRAM (or SRAM) and jump right into it.

The IROM on the AT89C51RC is being used as a bootloader, only being used to upload data into the NVRAM. If I breaks the self-imposed limit on using only through-hole parts I would even throw in an FT245 as the USB interface chip instead of ATtiny2313 + V-USB.

[legacy]

with XRAM and XROM pointing to the same location

PSEN mixed with WR ?

[legacy]

guys, so, pascal 51 actually exists 

[technix]

with XRAM and XROM pointing to the same location

PSEN mixed with WR ?

PSEN (Read/Execute) mixed with RD. Yeah that is the point.