Poll

Do you use Verilog or VHDL?

I'm a pro and I use Verilog (or SystemVerilog)
13 (15.7%)
I'm a hobbyist and I use Verilog (or SystemVerilog)
22 (26.5%)
I'm a pro and I use VHDL
17 (20.5%)
I'm a hobbyist and I use VHDL
20 (24.1%)
I use both
3 (3.6%)
What's all this Verilog/VHDL nonsense anyway?
8 (9.6%)

Total Members Voted: 82

Author Topic: Verilog or VHDL?  (Read 28795 times)

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Offline legacy

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Re: Verilog or VHDL?
« Reply #100 on: August 22, 2016, 11:44:22 am »
Code: [Select]
u_integer/positive <= to_integer(unsigned(std_logic_vector));

the above will look like

Code: [Select]
u_integer/positive <= std_logic_vector_to_u_integer(std_logic_vector,size);

which makes less confusion and it's absolutely clear
(even if the operator's name is too long)
 

Offline nctnico

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Re: Verilog or VHDL?
« Reply #101 on: August 22, 2016, 11:57:40 am »
What happened to 'don't use std_logic_vector'?
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: Verilog or VHDL?
« Reply #102 on: August 22, 2016, 12:26:59 pm »
in case, tell me alternatives
 

Offline legacy

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Re: Verilog or VHDL?
« Reply #103 on: August 22, 2016, 12:28:52 pm »
(and don't forget that ghdl has some problems with the unsigned type
when it needs to be interfaced with C-modules, don't ask me why  :-// )
 

Offline legacy

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Re: Verilog or VHDL?
« Reply #104 on: August 22, 2016, 01:08:10 pm »
also the following doesn't work under ghdl

Code: [Select]
library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

...
  constant XLEN : integer := 32;
  subtype  cpuWord is std_logic_vector(XLEN -1 downto 0);
...

      when alu_add =>
        res  <= opa + opb + (getStdLogicVectorZeroes(XLEN-1) & cin);

Code: [Select]
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

those libraries are NOT defined in ghdl and can't be used easily
therefore the "+" operator is not defined for std_logic_vector
and the attempt to simulate "opa + opb" will result an error

instead you need to use

Code: [Select]
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

along with the following ugly code

Code: [Select]
        when alu_add =>
          result  <= std_logic_vector
                  (
                  unsigned(opa) + unsigned(opb) +
                  unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)
                  );
          work <= std_logic_vector
                  (
                  unsigned("0" & opa) + unsigned("0" & opb) +
                  unsigned(getStdLogicVectorZeroes(XLEN-1) & cin)
                  );

in this case "unsigned(opa) + unsigned(opb)" is allowed
because the "+" operator is defined along with unsigned
but the result needs to be std_logic_vector  :palm: :palm: :palm:


both the above pieces of code come from OpenCores
therefore I assume it's a common trouble  :-//


edit:
Code: [Select]
entity ALU_arithmetic is
    Port
    (                   
      enable : in  std_logic;
      -----------------------
      opa    : in  cpuWord;
      opb    : in  cpuWord;
« Last Edit: August 22, 2016, 01:14:26 pm by legacy »
 

Offline nctnico

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Re: Verilog or VHDL?
« Reply #105 on: August 22, 2016, 01:23:33 pm »
in case, tell me alternatives
The signed and unsigned types. If a signal represents a number of index (and surprisingly many multi bit signals do) you should not use std_logic_vector. And yes, do use use ieee.numeric_std.all;
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline Pack34

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Re: Verilog or VHDL?
« Reply #106 on: August 22, 2016, 01:31:21 pm »
I'm a professional and use both.

For maintaining older projects originally written by someone else I use VHDL. However, for newer projects I prefer to use Verilog.

I personally prefer Verilog because I just feel more comfortable using it. It's what I was trained on in college and grad school and I feel it's a bit more readable but that's most likely just because I have more experience with it.
 


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