Author Topic: JTAG is JTAG is JTAG  (Read 31908 times)

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Offline Crazy ApeTopic starter

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JTAG is JTAG is JTAG
« on: November 28, 2013, 02:57:48 pm »
JTAG is JTAG is JTAG............

.......as long as you can avoid the vendor supplied programming utility.

It seems that every chip vendor requires you to use 'their own' - expensive - JTAG programmer to program the chips they produce. While this may be pocket change for some folks, some of us prefer to save a dollar or ten where ever possible.

While a hobbyist may not want to spend money on yet another programming device, other reasons exist for not wanting to use the vendors programming software/tool. You might have several devices, all from different vendors, and all sitting on the same JTAG chain. Programming each device with it's vendors software and associated JTAG programmer can become a real pain.

Myself, I don't like the artificial limits that chip companies impose on their customers. The first (only) programmer I bought was an Altera USB Blaster (likely some kind of clone actually), this was great for the large Altera CPLD I was playing with but I also had a small Xilinx device as well.

Open Source to the rescue with UrJTAG.
Link: http://urjtag.org/

UrJTAG allows you to use most JTAG programmers with a variety of devices from different vendors.

The key to this is to export your design as an .svf file, most vendors have this as an option in their software.

This is an example of programing a 'Xilinx' xc3s500e FPGA with an 'Altera' USB Blaster.

Quote
CrazyApe ~ # jtag

UrJTAG 0.10 #2039
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable UsbBlaster
Connected to libftdi driver.
jtag> detect
IR length: 14
Chain length: 2
Device Id: 11010101000001000110000010010011 (0xD5046093)
  Manufacturer: Xilinx (0x093)
  Part(0):      xcf04s (0x5046)
  Stepping:     13
  Filename:     /usr/share/urjtag/xilinx/xcf04s/xcf04s
Device Id: 01000001110000100010000010010011 (0x41C22093)
  Manufacturer: Xilinx (0x093)
  Part(1):      xc3s500e_fg320 (0x1C22)
  Stepping:     4
  Filename:     /usr/share/urjtag/xilinx/xc3s500e_fg320/xc3s500e_fg320
jtag> svf /mnt/EDA-Drive/Work/FPGA/xilinx/RotoFractal/default.svf
warning: USB-Blaster frequency is fixed to 12000000 Hz
jtag> quit
CrazyApe ~ #

« Last Edit: November 28, 2013, 03:27:23 pm by Crazy Ape »
 

Offline MrAureliusR

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Re: JTAG is JTAG is JTAG
« Reply #1 on: November 28, 2013, 03:05:22 pm »
Yeah I just downloaded this software, looks incredibly cool! I'm probably going to pick up a Xilinx JTAG programmer off someone I know locally, good to know I can apply it in many ways!

On that note, if you scour eBay, you'll notice most of the Chinese knockoff JTAG programmers look suspiciously similar, just different stickers on the outside. There's even one with Xilinx, Altera and Lattice logos on the side that claims to do all three!
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Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #2 on: November 28, 2013, 03:18:49 pm »
Yeah I just downloaded this software, looks incredibly cool! I'm probably going to pick up a Xilinx JTAG programmer off someone I know locally, good to know I can apply it in many ways!

On that note, if you scour eBay, you'll notice most of the Chinese knockoff JTAG programmers look suspiciously similar, just different stickers on the outside. There's even one with Xilinx, Altera and Lattice logos on the side that claims to do all three!

Yeah, I've seen the flood of JTAG programmers of all sorts on ebay and the Chinese sites. But what I have works well for what I do. It adds two mouse clicks (switch to UrJTAG window and back again) and generally two key presses (up arrow and enter - assuming I'm repeating the same command) which adds about 1/4 of a second to my work flow. Though the triple mode programmers look like they could be handy.
 

Offline mikeselectricstuff

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Re: JTAG is JTAG is JTAG
« Reply #3 on: November 28, 2013, 03:46:11 pm »
JTAG itself is standard, however there are non-standards at both ends - at the PC end,  there is no standard API, although now that FTDI supply a JTAG API for their hi-speed USB parts, there is no excuse for anyone inventing a new one, and some manufacturers (e.g. Lattice) support programming via a FTDI chip.
At the other end, how JTAG is used to program devices is typically very part-specific and often undocumented.
This is how companies like Segger can get away with charging such high proces for their JTAG hardware
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Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #4 on: November 28, 2013, 04:31:47 pm »
JTAG itself is standard, however there are non-standards at both ends - at the PC end,  there is no standard API, although now that FTDI supply a JTAG API for their hi-speed USB parts, there is no excuse for anyone inventing a new one, and some manufacturers (e.g. Lattice) support programming via a FTDI chip.
At the other end, how JTAG is used to program devices is typically very part-specific and often undocumented.
This is how companies like Segger can get away with charging such high proces for their JTAG hardware

I agree with all the above, lots of undefined cruft sitting on to of a well defined standard, the being the JTAG state machine.

Being able to export to an .svf file were possible at least gets away of the vendors proprietary binary format.

As for the communication API between the PC and the JTAG programmer, while it transports JTAG commands to the JTAG state machine in the device, it seems to be more about locking you (or your product design) into a particular vendor than anything to do with improving JTAG usage. Though if we're using non vendor software with a choice of programmer API's, this is much less of an issue.

What I was getting at with my post was that the JTAG state machine is standard everywhere and there are numerous ways to drive it, not just via the vendors tools.
 

Offline legacy

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Re: JTAG is JTAG is JTAG
« Reply #5 on: November 28, 2013, 04:46:16 pm »
it there a way from an embedded router (linux/mips) with usb to download a bitstream (through Xiling-usb-blaster) to a Xiling fpga ?
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #6 on: November 28, 2013, 05:09:36 pm »
it there a way from an embedded router (linux/mips) with usb to download a bitstream (through Xiling-usb-blaster) to a Xiling fpga ?

If you have root access to the router and a way of compiling code for it, then I don't see why it wouldn't work.

You'll need the following (and whatever dependencies they have):
The open source FTDI drivers: http://www.intra2net.com/en/developer/libftdi
LibUSB (may already be present depending on router): http://www.libusb.org
UrJTAG: http://urjtag.org
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #7 on: November 28, 2013, 05:10:00 pm »
There are still other options.
If you have a half reasonable micro-controller handy (and know how to wield it) take a look at Xilinx XAPP058.
http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf
 

Offline legacy

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Re: JTAG is JTAG is JTAG
« Reply #8 on: November 28, 2013, 05:13:39 pm »
FTDI is not x86 binary only ?
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #9 on: November 28, 2013, 05:17:43 pm »
FTDI is not x86 binary only ?

There is more than one set of FTDI drivers, I linked to the Open Source drivers, they will compile on non-Intel architectures.
 

Online nctnico

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Re: JTAG is JTAG is JTAG
« Reply #10 on: November 28, 2013, 08:42:05 pm »
IMHO JTAG sucks pretty bad. It looks like a nice piece of asfalt but you need a different kind of car for each destination. Managers don't seem to care because they usually think JTAG is standard so they only need one JTAG dongle to program everything.

I try to avoid it whenever possible especially on embedded platforms. Early in my career the design team I was part of decided to program a bunch of Xilinx FPGAs on a PCB through JTAG from a microcontroller. JTAG is standard so how hard can that be? I got the task of actually getting it to work. It turned out to be an much bigger project than anticipated. It appeared Xilinx had some semi documented protocol where packets send over JTAG would set the FPGA in certain modes. I got it working mostly through trial and error (including a fried-by-software FPGA!). A board respin with different FPGAs (the brand new Spartan 2E instead of Spartan2) caused the programming to stop working. With more trial and error I got it working again.

From that moment I used serial programming options whenever available.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline legacy

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Re: JTAG is JTAG is JTAG
« Reply #11 on: November 28, 2013, 08:55:21 pm »
A board respin with different FPGAs (the brand new Spartan 2E instead of Spartan2) caused the programming to stop working. With more trial and error I got it working again.

why ?
 

Offline EEVblog

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Re: JTAG is JTAG is JTAG
« Reply #12 on: November 28, 2013, 08:55:46 pm »
This is how companies like Segger can get away with charging such high proces for their JTAG hardware

JTAG pogrammers have always been high priced because their primary market has been professionals for whom cost is not a major factor, JTAG enabled devices haven't really penetrated much into the low cost scene like the PIC/AVR/MSP/WHATEVER programmers have captured. And for those that have (Xilinx/Altera FPGA's + ARM processors), you can get programmers delivered for under $10 on ebay.
And the professionals also use JTAG for production boundry scan testing etc, not just as a programmer. so the software tools get a lot more complicated and expensive than just programming software.
 

Offline legacy

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Re: JTAG is JTAG is JTAG
« Reply #13 on: November 28, 2013, 09:21:42 pm »
Jtag for Flash programming may be done with cheap jtag devices (< $50)
• Flash programming algorithm controls our chip output pin-s state using JTAG EXTTEST mode
• Pins logic state is set to 0,1 or high impedance state according to signal diagrams in FLASH chip data sheet


but Step-by-step debugging sees two corner cases of JTAG software debug implementation

First case: software "speaks" with JTAG device in terms of TAP controller FSM states; bit-vectors need to be shifted in and out, to and from registers of TAP controller
• Physical connection to TAP controller is made in software bit-banging mode
• Optimized access to TAP controller when intellectual JTAG cable accelerates JTAG operations at physical levels
Example: Olimex-USB-OCD + OpenOCD for ARM (still cheap devices < $50)

- Second case: software "speaks" with JTAG device in terms of debugged process, such as "next instruction", "step-in", "step-over", "show registers, they go for the description of "Optimized TAP controller with high throughput and advanced features"
Example: Abatron BDI 2000 (expensive > $400 devices, and it may costs $2000 or more, BDI 2000 is very very expensive)
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #14 on: November 28, 2013, 09:22:47 pm »
IMHO JTAG sucks pretty bad. It looks like a nice piece of asfalt but you need a different kind of car for each destination. Managers don't seem to care because they usually think JTAG is standard so they only need one JTAG dongle to program everything.

I try to avoid it whenever possible especially on embedded platforms. Early in my career the design team I was part of decided to program a bunch of Xilinx FPGAs on a PCB through JTAG from a microcontroller. JTAG is standard so how hard can that be? I got the task of actually getting it to work. It turned out to be an much bigger project than anticipated. It appeared Xilinx had some semi documented protocol where packets send over JTAG would set the FPGA in certain modes. I got it working mostly through trial and error (including a fried-by-software FPGA!). A board respin with different FPGAs (the brand new Spartan 2E instead of Spartan2) caused the programming to stop working. With more trial and error I got it working again.

From that moment I used serial programming options whenever available.

Setting up certain modes on the target sounds pretty much like standard JTAG state machine manipulation to me. If you try to treat JTAG as some kind of serial protocol, you'll come to grief quite quickly.
This is the beast you were dealing with:
 

Offline legacy

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Re: JTAG is JTAG is JTAG
« Reply #15 on: November 28, 2013, 09:37:56 pm »
From the point of view of the Electrical Characteristics JTAG is an interface with special four/five pins
• TDI (Test Data In)
• TDO (Test Data Out)
• TCK (Test Clock)
• TMS (Test Mode Select)
• TRST (Test Reset) - optional

From a the point of fsm jtag is a TAP State Machine composed by these commands
• BYPASS 111...1 "all ones" command, register is filled with ones
• EXTTEST 000 ..0 "all zeros" command, connects "boundary scan" register between TDI and TDO
• SAMPLE 000...1 "one in last bit" command, connects 1-bit "bypass" register between TDI and TDO TAP behaves as transparent 1-bit shift register
-------- which may also have optional commands -------
• INTEST, places the IC in an internal boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO
• CLAMP, sets the outputs of an IC to logic levels determined by the contents of the boundary-scan reg & selects the bypass regto be connected between TDI and TDO
• HIGHZ, sets all outputs (including two-state and three-state types) of an IC to (high- impedance) state and selects the bypass register connected between TDI and TDO
• USERCODE, allows functional mode and selects the device register to be connected between TDI and TDO

From my (and debug Application) point of view Jtag is related to Boundary scan description language (BSDL) which is a subs to VHDL used to describe how JTAG (IEEE 1149.1) is implemented in a particular device, and a device to be JTAG compliant, it must have an associated BSDL file. Many IEEE Std 1149.1 tools already on the market support BSDL as a data input format. These tools offer different capabilities to customers implementing IEEE Std 1149.1 into their designs, including board interconnect automatic test-pattern generation (ATPG) and automatic test equipment (ATE).


So BSDL is/may be the problem !
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #16 on: November 28, 2013, 09:49:59 pm »
So BSDL is/may be  the problem !

Vendor tools are obviously the way to go if you have deep pockets, or need some function that's not met in open-source tools, but not everyone fits that category. 
That being said, vendors release BSDL files so I'm not sure why BSDL should be a problem. For instance, lets check the state of PAD63 on my xc3s500e die. It's an unused input with pulldown to ground, so it should be 0.

Quote
jtag> instruction SAMPLE/PRELOAD
jtag> shift ir
jtag> shift dr
jtag> dr
101101101101110110110111011011011011101101101101110110110110111011011011011101101101101110110110110111011011011011101101101101111111111111111111111111011011111111111111111111111111111111111111111111111111111111111111011011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110110111011011011011011110110111011011011011011011011110110110110110111101101101101101111011011011011011110110111011011011011011011011110110100 (0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000DBDB6DEDDB6DB7B4)
jtag> print chain
 No. Manufacturer              Part                 Stepping Instruction          Register                       
-------------------------------------------------------------------------------------------------------------------
   0 Xilinx                    xcf04s               13       BYPASS               BYPASS                         
*  1 Xilinx                    xc3s500e_fg320       4        SAMPLE/PRELOAD       BSR                             
jtag> get signal PAD63
PAD63 = 0
jtag>

No problems playing with the boundary scan register here.  :)
 

Online nctnico

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Re: JTAG is JTAG is JTAG
« Reply #17 on: November 28, 2013, 10:30:15 pm »
A board respin with different FPGAs (the brand new Spartan 2E instead of Spartan2) caused the programming to stop working. With more trial and error I got it working again.

why ?
Because the programming sequence for the 2E was slightly different from the 2. But thats ancient history now. AFAIK the Spartan2E is already obsolete.

@Grazy Ape: Now try to do something with that statemachine... JTAG is like SPI, I2C, UART, etc: a physical layer interface. If you know which commands to send you can access the chip otherwise you can't.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #18 on: November 28, 2013, 10:41:05 pm »
@Grazy Ape: Now try to do something with that statemachine... JTAG is like SPI, I2C, UART, etc: a physical layer interface. If you know which commands to send you can access the chip otherwise you can't.

The commands are listed in the BSDL file, and you can also get a good idea of their use by looking at the first page of any .svf file targeted at the device.
 

Offline MrAureliusR

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Re: JTAG is JTAG is JTAG
« Reply #19 on: November 29, 2013, 03:08:01 am »
Question about Bus Pirate and JTAG (if anyone knows about it):

I'm using Kubuntu Linux 13.04, just FYI. I've also tried to compile OpenOCD for Cygwin but it fails because of syntax errors, outdated files, etc. It just doesn't seem well-supported in Cygwin anymore. So I've finally got OpenOCD set up in Linux -- I've got the buspirate.cfg file correctly written, but now I'm a bit lost. I understand that once the OpenOCD 'server' is running you have to connect to it using ssh, telnet or similar.

How exactly is this done? loopback/127.0.0.1? The tutorials on the Dangerous Prototypes website seem to all be very old, and I know it's not a super-supported feature, but I'd just like to be able to use the Pirate for all the interfaces I possibly can.

Thanks!

PS When my Xilinx dev kit shows up I will do a thread about it. I have a feeling it's going to be very good value for money. Also, trying to find Verilog resources for beginners -- recommendations anyone?
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Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #20 on: November 29, 2013, 03:54:15 am »
Question about Bus Pirate and JTAG (if anyone knows about it):

I'm using Kubuntu Linux 13.04, just FYI. I've also tried to compile OpenOCD for Cygwin but it fails because of syntax errors, outdated files, etc. It just doesn't seem well-supported in Cygwin anymore. So I've finally got OpenOCD set up in Linux -- I've got the buspirate.cfg file correctly written, but now I'm a bit lost. I understand that once the OpenOCD 'server' is running you have to connect to it using ssh, telnet or similar.

How exactly is this done? loopback/127.0.0.1? The tutorials on the Dangerous Prototypes website seem to all be very old, and I know it's not a super-supported feature, but I'd just like to be able to use the Pirate for all the interfaces I possibly can.

Thanks!

PS When my Xilinx dev kit shows up I will do a thread about it. I have a feeling it's going to be very good value for money. Also, trying to find Verilog resources for beginners -- recommendations anyone?

The manual says:
A human should interact with the telnet interface (default port: 4444) or via GDB (default port 3333).
http://openocd.sourceforge.net/doc/html/General-Commands.html

Lets give is a try  :D

Quote
CrazyApe ~ # telnet localhost 4444
Trying ::1...
telnet: connect to address ::1: Connection refused
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> version
Open On-Chip Debugger 0.8.0-dev-00020-g8890ce3-dirty (2013-06-05-16:37)
>

It works, just ignore the "telnet: connect to address ::1: Connection refused" message, it's an IPv6 connection attempt by my telnet.

So, this should work for you:
telnet localhost 4444
 

Offline MrAureliusR

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Re: JTAG is JTAG is JTAG
« Reply #21 on: November 29, 2013, 04:17:45 am »
Got it.  :clap: Problem now is I don't think the target config is quite right... man JTAG is powerful, though!
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Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #22 on: November 29, 2013, 04:19:32 am »
Got it.  :clap: Problem now is I don't think the target config is quite right... man JTAG is powerful, though!

What device are you targeting?
 

Offline MrAureliusR

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Re: JTAG is JTAG is JTAG
« Reply #23 on: November 29, 2013, 04:21:25 am »
TMS570LS04x TI Hercules ARM processor. There's a JTAG chain on this board, of about 3 or 4 devices I believe. If I use ti_calypso.cfg it actually does detect the chip, but then basically nothing actually works.

It's not a huge deal, it'd be cool to get it working, but I really just want to use this as a backup/possibly my only option for programming my Xilinx dev board.
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Offline Crazy ApeTopic starter

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Re: JTAG is JTAG is JTAG
« Reply #24 on: November 29, 2013, 04:31:20 am »
TMS570LS04x TI Hercules ARM processor. There's a JTAG chain on this board, of about 3 or 4 devices I believe. If I use ti_calypso.cfg it actually does detect the chip, but then basically nothing actually works.

It's not a huge deal, it'd be cool to get it working, but I really just want to use this as a backup/possibly my only option for programming my Xilinx dev board.


OK, the Hercules uses TI's ICDI (in-circuit debug interface) so you'll need to rebuild OpenOCD with --enable-ti-icdi   :(
See here for info, it's for Stellaris but both Stellaris and Hercules use ICDI so you should be good to go.
http://www.jann.cc/2012/12/11/getting_started_with_the_ti_stellaris_launchpad_on_linux.html#build-openocd-with-icdi-support

 


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