Kinetis MK66, 5v signal input to GPIO 5v no tolerant

[luiHS]

 
Hello

I need to connect 5v signals to the input ports of a Kinetis MK66 microcontroller, the ports are not 5v tolerant.

So far I have used an HEF4050 in SOIC, but when trying the CD4050 version in TSSOP I have problems, I think because the propagation time of this chip is quite high, over 140ns.

I found the 74LVC07, which has a much shorter propagation time, about 2ns, could be a solution. But on the other hand, I have read that the inputs of the MK66 have internally an ESD protective diode that I suppose cuts the signal if the current is limited.

My question is whether it would be enough to put serial resistors to the inputs of the ports to be able to connect 5v signals to the ports of this microcontroller. The alternative is to use a 74LVC07, but if I can do it with resistors  much better and cheaper.

Regards

[jaromir]

Can you use resistor divider? Something like 220R/330R, that should have output impedance ~130R, with typical input capacitance of MCU inputs (10pF or thereabouts) should be considerably faster than CD4050.

[Ian.M]

@luiHS,
Absolutely *NOT*.  The quoted text (image) says there is *ONE* clamping diode to Vss (aka Gnd, 0V), and *NONE* to Vdd.  It doesn't say at what voltage that diode will Zener at therefore it doesn't offer you *ANY* encouragement to use it for positive clamping.

If your 3.3V supply rail has a greater minimum load than the maximum possible clamping current from *ALL* your 5V inputs, you could try series resitors + external small signal  Schottky clamping diodes to Vdd.

Can you use resistor divider? Something like 220R/330R, that should have output impedance ~130R, with typical input capacitance of MCU inputs (10pF or thereabouts) should be considerably faster than CD4050.

That's good if you can stand the power consumption.  However if you need to retain the speed and decrease power consumption by increasing the divider resistors, you may need a small speedup cap across the upper resistor.  Characterize the input capacitance of the pin (+ track) and scale the speedup cap in proportion to the resistor ratio.   Don't go too big - more than a couple of tens of pF will transiently overvoltage the input.  Don't try to 'scope it and see' unless you've got a *very* low capacitance active probe.

[luiHS]

 
Ok, I understand.
This is my current schematic.

Can I remove the CD4050, and add resistors in parallel with the 68pf capacitors to do the resistor dividers ?, serial resistors modify value to 330 ohm, and the new resistors to GND with value 220 ohm.

[Ian.M]

No.  Get rid of the caps.  They do sweet FA for any noise below the high VHF or even UHF band and are severely loading your CD4050 outputs.  That alone may fix your problem.

If you really want to try the dividers and your 5V signals will tolerate a 550R load, remove the CD4050 and the caps and put the 330R resistors on what were the caps' pads.

P.S. [SNARK] Why does your schematic show the '4050 outputs being back driven from the named nets?  Net label signal directions are *IMPORTANT* to schematic readability - please take the time to get them right!  [/SNARK]

[SiliconWizard]

If you want to use a true level shifter, use a SN74LVC245A. You can use the 74LVC1T45 if you need it as a single gate.
They have 5V-tolerant input and a wide operating voltage range. Just power them with your MCU's IO supply (VDD if there's not separate IO supply).

[luiHS]

If you want to use a true level shifter, use a SN74LVC245A. You can use the 74LVC1T45 if you need it as a single gate.
They have 5V-tolerant input and a wide operating voltage range. Just power them with your MCU's IO supply (VDD if there's not separate IO supply).

It is an option, also the 74LVC07APW,112.

Reviewing the data sheet of 74LVC07APW,112,  I see that it says that the output is open drain. This is useful for connecting to the GPIO of the microcontroller, or may I need to add some pullup or pulldown resistors ?.

If output resistors are needed, I can also enable the internal pullup-pulldown resistors of the Kinetis MK66 in each GPIO.

[PCB.Wiz]

So far I have used an HEF4050 in SOIC, but when trying the CD4050 version in TSSOP I have problems, I think because the propagation time of this chip is quite high, over 140ns.

I found the 74LVC07, which has a much shorter propagation time, about 2ns, could be a solution.

How fast does this need to be ?
If you want best speed, and lowest power, a Dual Supply voltage translator is the best solution.
Also common, is designs using series MOSFETS*, which give bi directional links, and have low impedance on the rise times, then go open drain at higher voltages.

* Logic Level NMOSFET, is connected Source to 3v3 IO side, Drain to 5V IO side with pullup to 5V, and Gate to 3v3 rail.  Either side going low, pulls the other side low.

[luiHS]

So far I have used an HEF4050 in SOIC, but when trying the CD4050 version in TSSOP I have problems, I think because the propagation time of this chip is quite high, over 140ns.

I found the 74LVC07, which has a much shorter propagation time, about 2ns, could be a solution.

How fast does this need to be ?
If you want best speed, and lowest power, a Dual Supply voltage translator is the best solution.
Also common, is designs using series MOSFETS*, which give bi directional links, and have low impedance on the rise times, then go open drain at higher voltages.

* Logic Level NMOSFET, is connected Source to 3v3 IO side, Drain to 5V IO side with pullup to 5V, and Gate to 3v3 rail.  Either side going low, pulls the other side low.

Now it is working with HEF4050 and it works well, it has a propagation speed of 120ns, although when I use the CD4050 I have problems, it is slower, 140ns. My idea is to replace the 4050 with a 74LVC07APW with 2ns of propagation speed or an SN74LVC245A with 4ns.

I can't change the supply voltage, everything must work at 5v. And I want to keep the circuit as simple as possible, so I must use a single chip or resistor divider.

[SiliconWizard]

If propagation speed is a concern here, I would recommend a totem-pole output config instead of an open-drain one (thus eg. the LVC245 over the LVC07.)

With an open-drain output, you'll have to use pull-up resistors. This will create asymetrical rise and fall times. The rise time will be in the order of the R.C constant, typically in the order of the pull-up resistor value times the input capacitance of the GPIOs. To get an idea, say you use 10kohm pull-ups (weak internal pull-ups in most MCUs GPIOs are typically even significantly higher!), and assuming an input capacitance of 10pF (reasonable figures), that's a rise time in the order of 100ns. Keep that in mind.