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Electronics => Microcontrollers => Topic started by: jtronix on April 13, 2016, 11:25:14 am

Title: L1 cache causing error in bootloader
Post by: jtronix on April 13, 2016, 11:25:14 am
I'm working with renesas RZ A1H cortext A9 processor and i have one problem with Boot loader. In boot loader if L1 cache is initialize then it wont jump to the user application and it stuck after jump function. also I'm initializing L1 cache again in my user application.
Everything works fine if L1 cache is not initialize in bootloader.
Title: Re: L1 cache causing error in bootloader
Post by: tszaboo on April 13, 2016, 11:29:06 am
If this is just a "public announcement", then I would like to add, that the ART accelerator, which is a cache to the Flash on the STM32 MCUs, also cause issues when bootloading.
I would just turn off any caching on any architecture when bootloading.
Title: Re: L1 cache causing error in bootloader
Post by: jtronix on April 13, 2016, 11:33:28 am
How to overcome this issue of cache?? In bootloader i need cache to perform operation faster but it wont booting my application.
Is there any steps that needed before jumping to the user application???
Title: Re: L1 cache causing error in bootloader
Post by: tszaboo on April 13, 2016, 11:47:16 am
On that MCU the issue was:
10 The MCU was containing code.
20 We overwrote the Flash.
30 We were expecting that the new code will be excecuted, but the old was, since it was in the cache

The solution was to 25 flush the cache. Or to turn it off if possible.


Title: Re: L1 cache causing error in bootloader
Post by: andersm on April 13, 2016, 01:22:03 pm
On some architectures, the caches contains random garbage on powerup and needs to be cleared before being enabled.
Title: Re: L1 cache causing error in bootloader
Post by: jtronix on April 14, 2016, 04:09:21 am
do you have cache flush assembly code for cortex A9 processor or programming guide ?
Title: Re: L1 cache causing error in bootloader
Post by: andersm on April 14, 2016, 05:11:46 pm
You can probably find code easily on the net (eg. any open-source OS that supports the Cortex-A9). The cache maintenance operations are performed via CP15, and are documented in the ARMv7-A architecture reference manual, and the Cortex-A9 technical reference manual for the core-specific bits.