Author Topic: Lattice announces MachXO3 cpld/fpga hybrid  (Read 2041 times)

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Offline marshallh

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Lattice announces MachXO3 cpld/fpga hybrid
« on: September 26, 2013, 01:39:26 am »
Seems they put on SERDES into a super low cost fpga. MIPI, PCIe, GbE. 3.125G

They still have the ECP4 in the works. It was going to be released last years on 65nm but was pulled and any trace was wiped off Lattice' website.
From what I see it will launch coinciding with the release of Diamond 3.0

Quote
Lattice's MachXO(TM) and MachXO2(TM) families of instant-on, non-volatile programmable devices have set the standard for providing system architects complete, low-cost options to expand general purpose I/O, bridge interfaces and minimize total system power.

Leveraging a low power architecture built on 40nm process technology to deliver lower cost with increased performance for power sensitive applications, the new MachXO3 family delivers a new set of capabilities that enable system engineers to do even more in a smaller footprint.

The new 640-to-22K logic-cell family makes use of the latest in package technology to not only deliver tiny 2.5x2.5mm wafer-level chip-scale packaging, but also 540 I/O count devices, as well as devices with 3.125Gbps SERDES capabilities to cover the full spectrum of bridging and interface requirements in consumer, industrial, communications, automotive, and compute markets.

Supported by Lattice Diamond(R) software, as well as IP and application expertise both in-house and by third parties, the MachXO3 FPGA family is a complete solution that delivers:


Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 

Offline marshallh

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Re: Lattice announces MachXO3 cpld/fpga hybrid
« Reply #1 on: September 26, 2013, 01:50:08 am »
Seems Lattice' website is completely swamped. I was barely able to get on.

Anyway I predict this will probably require Diamond subscription and licensing of the higher level IP layers to make the protocols work.
The generic 8b/10b serdes may be there but it will just be exposed to the user logic in a PIPE-like fashion. Same with the ECP3, you need to license this functionality to use the protocols.

Something they didn't mention is 3g SATA, which should be perfectly doable with the hardware they have. It's just different protocol-wise but shares the same PHY layer as pcie/usb3.
Verilog tips
BGA soldering intro

11:37 <@ktemkin> c4757p: marshall has transcended communications media
11:37 <@ktemkin> He speaks protocols directly.
 


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