Question about Quartus

[mn]

I have written a VHDL code in Quartus and have compiled it without any error. I am able to view the schematic via Tools->Netlist Viewers->RTL Viewer

The questions are
1- The RTL schematic shows the gate level. I want to see the LUTs in the LABs that were used to implement the design. How can I do that?
2- Is there any way to view the placed and routed design inside the device editor?

I see those things in Xilinx ISE. Any idea about them?

[jahonen]

1. You can see LUTs in technology map viewer. That should show the contents of the LUTs.

2. Chip Planner shows where the design elements physically are.

Regards,
Janne

[mn]

1- I doubt if the technology map viewer really shows the LUTs. As you can see in the picture (post mapping), in each block the gate level is shown not the LUTs.

2- The chip planner shows the layout of the chip but there is no label for the objects. Also, I don't know where is my design on the chip. Please see the two pictures.

[jahonen]

Try using post fit technology map viewer, that should show LUTs.

The darkened blocks in zoomed out view of chip planner shows where populated blocks are. Try zooming there. Alternatively, you can use the node finder to locate your design objects.

Regards,
Janne

[mn]

Sorry but I don't see any "post fit". If you mean, "technology mapper viewer (post mapping)", then the picture I attached in my previous post is actually the post mapped one. It only shows the block diagram (at least this is what I see).

[Daixiwen]

What kind of information are you looking for exactly?
AFAIK the technology map viewer still shows you the design hierarchy but decomposes everything inside each block at the basic level: registers, LUTs, memory blocks and multipliers. What you show in your first screenshot looks like LUTs to me, with 4 inputs and one output each.

[Scrts]

If it shows a module, double click can go into it AFAIK. You will be able to go down as far as the primitives then.