Really sorry for resurrecting this, but I have discovered the answer and this happens to be one of the first google results. There are not one, but two VHDL flags that have to be set for everything to work. Running the following tcl commands on my project got synthesis to work (not sure about the editor...I'm using a scripted flow and avoid the Diamond editor at all costs):
prj_strgy set_value lse_vhdl2008=True
prj_strgy set_value syn_vhdl2008=True
I discovered these by seeing hints online that the strategy needed to be changed, running "prj_strgy list_option *", and setting all the VHDL 2008 options to true. I also looked in the .sty file to make sure I hadn't missed any.