Author Topic: Lattice iCE40 Bitstream Reverse-Engineered  (Read 20409 times)

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Offline wumpus

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #25 on: June 03, 2015, 11:17:45 am »
Linux is successful because so many people have a use for it. the FPGA area is just too specialist for enough people to be interested, and the vast majority of users don't care what flavour of tools they need to use to do the job.
Many people would disagree. Due to various reasons (crowdfunding, distrust, scaling limits of CPUs among others), interest in open source hardware has picked up enormously recently.

The unavailability of general, open source FPGA tooling has always been a limiting factor there. Instead of applying tunnel vision to current (sort of) happy users of vendor tools, take a wider view. This can open up completely new markets.

There is nothing inherently esoteric or specialist about programmable logic, it could be said to be more fundamental than programming CPUs. But the bulky, hard to install, restrictively licensed tools have kept many people from even reaching the "hello world" phase - see the Parallela forums for enough examples, even if they have an FPGA available and are interested.

A freely available "gcc for FPGA" could make a huge difference here, smash down the adoption barrier. And one look at gcc (and clang) is enough to be convinced that the open source community is able to build huge, complex code generation pipelines. There is a lot of specialist knowledge represented.

Just as in a compiler, the chief part of the pipeline is generic. Place and route, seen abstractly, is a matter of having a correct definition of the units and connections of the target hardware then optimizing within those constraints. Even if the result is less optimized for a specific vendor, the generality and availability is a great boon for other applications (the same could be said about vendor compilers versus open source compilers).

Anyhow, arguing about this is useless. We'll see where this goes. I'm excited about it, at least.
 

Offline Mechanical Menace

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #26 on: June 03, 2015, 12:07:25 pm »
Bookmarked the IceStorm page. Amazing work Clifford, thanks. I can see this (and supported FPGAs) becoming very popular in the admittedly small homebrew computer and cpu scene before the year's out.
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Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #27 on: June 03, 2015, 12:25:21 pm »
Linux is successful because so many people have a use for it. the FPGA area is just too specialist for enough people to be interested, and the vast majority of users don't care what flavour of tools they need to use to do the job.
Many people would disagree. Due to various reasons (crowdfunding, distrust, scaling limits of CPUs among others), interest in open source hardware has picked up enormously recently.

The unavailability of general, open source FPGA tooling has always been a limiting factor there.
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.

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Offline daqq

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #28 on: June 03, 2015, 12:41:27 pm »
Quote
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.
To be fair, the bigger devices are supported only by the costly versions of stuff - atleast for Xilinx. Dunno about the rest, Altera, erm, Intertra?.

I never really got this - what's the point of not publishing stuff like this? From a chip manufacturers point of view it seems the best course of action would be to ensure that ALL of my tools area available to everyone, free of charge. Or atleast MASSIVELY support open source initiatives like this.

The availability of free or cheaply priced tools is a big issue for me, I assume the same goes for others.
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Offline Mechanical Menace

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #29 on: June 03, 2015, 12:42:17 pm »
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove.

I could use this on a none x86 cpu and (with a lot of learning) port it to an OS that isn't Windows or Linux. If you can't see some possibilities opening up there, no matter how niche, that's a bit of a lack of imagination.
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Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #30 on: June 03, 2015, 01:03:52 pm »
Quote
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.
To be fair, the bigger devices are supported only by the costly versions of stuff - atleast for Xilinx. Dunno about the rest, Altera, erm, Intertra?.

I never really got this - what's the point of not publishing stuff like this? From a chip manufacturers point of view it seems the best course of action would be to ensure that ALL of my tools area available to everyone, free of charge. Or atleast MASSIVELY support open source initiatives like this.

The availability of free or cheaply priced tools is a big issue for me, I assume the same goes for others.
The big-parts issue isn't really an issue here as we're talking parts with multi-hundred dollar price tags, in big BGA packages which need umpteen PCB layers to route. If you're making that kind of investment, a few $k on tools is chickenfeed. I suspect the reason for this is that they can use it to subsidise providing free tools to lower-end users.
Quote
I could use this on a none x86 cpu and (with a lot of learning) port it to an OS that isn't Windows or Linux. If you can't see some possibilities opening up there, no matter how niche, that's a bit of a lack of imagination.
I'm not saying that there aren't some niche situations where it might be interesting, just that these would be the exception, and existing tools are just fine for the vast majority of users, so the existence of OSS tools is a minimal benefit, to a few people.

The reason FPGAs aren't used very widely is nothing to do with tools, it's simply that they are only needed in niche applications. Availability of OSS tools won't change that.


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Offline Mechanical Menace

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #31 on: June 03, 2015, 01:22:23 pm »
The reason FPGAs aren't used very widely is nothing to do with tools, it's simply that they are only needed in niche applications. Availability of OSS tools won't change that.

In the hobbyist domain I'd say how overwhelming the tools can be is a serious barrier to entry. Something like this could lead to an Arduino style revolution (it has had it's upsides) for FPGAs.
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Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #32 on: June 03, 2015, 02:29:31 pm »
The reason FPGAs aren't used very widely is nothing to do with tools, it's simply that they are only needed in niche applications. Availability of OSS tools won't change that.

In the hobbyist domain I'd say how overwhelming the tools can be is a serious barrier to entry. Something like this could lead to an Arduino style revolution (it has had it's upsides) for FPGAs.
No it won't. Most hobbyists have no use for FPGAs.
Although they are huge and clunky, you can install and use an existing FPGA toolchain pretty easily. The biggest hurdle by far is getting your head round using an HDL. That is where there is definitely scope for interesting things to be done, and that doesn't need anyone to spend time reinventing the wheel with the back-end tools as any "easy-to-use" front-end can output HDL or RTL to the existing toolchain.
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Offline wumpus

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #33 on: June 03, 2015, 03:20:54 pm »
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.
You're quite quick to call someone else's experience nonsense, aren't you? I don't understand why you feel so strongly against this. Likely, in 1987 people like you were arguing against Richard Stallman for starting gcc.

It's not just the cost that is problematic, it is also the license restrictions to distribution. Distributing, say, a VM or docker image with ready-made FPGA toolchain is usually not allowed. Neither is offering an automatic 'build server' for bitstreams. This is the problem Parallela bumped against, as well as some educational projects.

Quote
That is where there is definitely scope for interesting things to be done, and that doesn't need anyone to spend time reinventing the wheel with the back-end tools as any "easy-to-use" front-end can output HDL or RTL to the existing toolchain.
The one doesn't exclude the other. There's many people working on different projects...
« Last Edit: June 03, 2015, 03:24:25 pm by wumpus »
 

Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #34 on: June 03, 2015, 03:48:46 pm »
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.
You're quite quick to call someone else's experience nonsense, aren't you?
Yes, when it's obvious  :D
Quote
I don't understand why you feel so strongly against this. Likely, in 1987 people like you were arguing against Richard Stallman for starting gcc.
gcc is not a reasonable comparison. The potential user base is orders of magnitude smaller, and there are currently tools available at no cost that are perfectly adequate for the majority of that user base.
Quote

It's not just the cost that is problematic, it is also the license restrictions to distribution. Distributing, say, a VM or docker image with ready-made FPGA toolchain is usually not allowed. Neither is offering an automatic 'build server' for bitstreams. This is the problem Parallela bumped against, as well as some educational projects.
and how many people is that actually useful for?

Quote

That is where there is definitely scope for interesting things to be done, and that doesn't need anyone to spend time reinventing the wheel with the back-end tools as any "easy-to-use" front-end can output HDL or RTL to the existing toolchain.
The one doesn't exclude the other. There's many people working on different projects...
[/quote]
True but given a limited number of available man-hours, my argument is simply that those hours would be more useful to more people if they were spent making new front-end tools and new design flows than reinventing stuff that already exists in a form that is perfectly fine for the vast majority of potential users, and will get updated by the manufacturers for new devices long after OSS projects have stalled and been abandoned.
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Offline Muxr

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #35 on: June 03, 2015, 04:00:23 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream. Decreasing the barrier of entry and streamlining the whole process. There is definitely room and demand for it. But not really for hardware design, more for performance computing.

I have to agree though for hardware design, it would be hard for a FOSS project to reach the quality and functionality of what's already provided by the FPGA manufacturers for free.
« Last Edit: June 03, 2015, 04:04:00 pm by Muxr »
 

Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #36 on: June 03, 2015, 05:32:52 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream.
And what would be the advantage of that over feeding it into the existing tools?
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Online blueskull

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #37 on: June 03, 2015, 05:58:02 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream.
And what would be the advantage of that over feeding it into the existing tools?

OS toolchain is important in academic and niche "open source belief" users. For most everyday users, I'd rather use vendor provided toolchain.

For the MyHDL things, I prefer it can translate its input into netlist or verilog. Reinventing wheels is never a good thing, unless you have a completely new concept and breakthrough.
 

Offline Muxr

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #38 on: June 03, 2015, 06:54:46 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream.
And what would be the advantage of that over feeding it into the existing tools?
Automated deployment for cloud compute. I think things are about to get interesting in the FPGA and x86 server market. With Intel buying Altera I could see an FPGA with x86 cores, used for hw acceleration of your compute clusters.

Sort of how OpenCL is being used, except FPGA can offer distinct advantages, like low latency. Opening the bitstream for this use would help adoption since most of your cloud outhere runs on Linux and FOSS stack.

It wouldn't really change how one designs in FPGAs into their hardware, but it would open up FPGAs to new applications.
« Last Edit: June 03, 2015, 06:59:17 pm by Muxr »
 

Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #39 on: June 03, 2015, 06:58:26 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream.
And what would be the advantage of that over feeding it into the existing tools?
Automated deployment for cloud compute. I think things are about to get interesting in the FPGA and x86 server market. With Intel buying Altera I could see an FPGA with x86 cores, used for hw acceleration of your compute clusters.

Sort of how OpenCL is being used, except FPGA can offer distinct advantages, like low latency.

It wouldn't really change how one designs in FPGAs into their hardware, but it would open up FPGAs to new applications.
Yes but in that example you'd almost certainly only be loading pre-compiled designs.
There is no way we'd ever see an OSS solution for a device that complex anyway.
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Offline Muxr

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #40 on: June 03, 2015, 07:00:05 pm »
An open sourced FPGA toolchain could have a benefit. For instance Python is heavily used in scientific field, this could leverage on demand use of higher level libs like MyHDL, and produce bitstream.
And what would be the advantage of that over feeding it into the existing tools?
Automated deployment for cloud compute. I think things are about to get interesting in the FPGA and x86 server market. With Intel buying Altera I could see an FPGA with x86 cores, used for hw acceleration of your compute clusters.

Sort of how OpenCL is being used, except FPGA can offer distinct advantages, like low latency.

It wouldn't really change how one designs in FPGAs into their hardware, but it would open up FPGAs to new applications.
Yes but in that example you'd almost certainly only be loading pre-compiled designs.
There is no way we'd ever see an OSS solution for a device that complex anyway.
Yes sorry I edited my response to include why I think it would be important. To help adoption, because most of your cloud runs Linux and the FOSS stack. Same reason Open CL exists over Cuda.
 

Online andersm

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #41 on: June 03, 2015, 07:05:07 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.

Offline hamster_nz

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #42 on: June 03, 2015, 07:07:54 pm »
Quote
Nonsense. There is no real barrier to using an FPGA in an OSHW project that an OS toolchain would remove. Everyone can access FPGA tools at minimal cost.
To be fair, the bigger devices are supported only by the costly versions of stuff - atleast for Xilinx. Dunno about the rest, Altera, erm, Intertra?.

I never really got this - what's the point of not publishing stuff like this? From a chip manufacturers point of view it seems the best course of action would be to ensure that ALL of my tools area available to everyone, free of charge. Or at least MASSIVELY support open source initiatives like this.

The availability of free or cheaply priced tools is a big issue for me, I assume the same goes for others.

The limits on size of 'free' versions isn't as big as it was even 5 years ago. Take for example Xilinx Vivado - the free version supports the XC7A200T part... 740 DSP blocks, quarter a million flip flips, 13Mb of on-chip RAM, 16 6Gb transceivers, PCIe, 500 I.O pins.

That is a LOT of stuff. What can't you build with that that doesn't need a team of full time engineers and enough financing to actually buy a license (which is rewarding Xilinx for their efforts, rather than just leaching :) )?
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Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #43 on: June 03, 2015, 09:26:33 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.
Reinventing what's already there is just wasted effort and will not do anything to improve the awfulness.
Unless of course someone can come up with some magic solution to place & route much, much more quickly.
Just imagine how useful it would be to use all the power sitting in GPUs to get near-instant update of a device when you change logic onscreen...


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Offline hamster_nz

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #44 on: June 03, 2015, 10:53:19 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.
Reinventing what's already there is just wasted effort and will not do anything to improve the awfulness.
Unless of course someone can come up with some magic solution to place & route much, much more quickly.
Just imagine how useful it would be to use all the power sitting in GPUs to get near-instant update of a device when you change logic onscreen...

Outside of hobby use it wouldn't be too useful at all. Unlike incremental software compilation, changes made higher up in a design force structural changes all the way through the design, and changes in the lowest levels could be unfairly constrained by what is already in place. It is most likely that any reasonable commercial design will use over 50% of some of the resources on a chip (otherwise you would use a smaller chip) and that doesn't leave much room for rip-up and place and route.

You would also have the problem that the performance of your design will depend on everything that has happened to the design beforehand - so you can't give a copy of the source to a co-worker and expect them to get the same results.

And I have to eat humble pie and say that Vivado isn't that bad (I didn't like it at first) - I'm currently working on a design using 90 DSP slices, running at 250MHz (about 0.13ns slack), and it build in under 5 minutes on my i3 laptop. Imagine if you were doing the equivalent of a PCB layout for ninety 100-pin chips and a few thousand bits of bubblegum logic... it is not just putting instructions and data into memory (which is all a s/w compiler has to).


And it is asking a bit much - Right I'm working on a design with 90 DSP splices, 18,000+ paths, running at 250MHz, with about 5% timing slack.
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Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #45 on: June 03, 2015, 11:01:25 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.
Reinventing what's already there is just wasted effort and will not do anything to improve the awfulness.
Unless of course someone can come up with some magic solution to place & route much, much more quickly.
Just imagine how useful it would be to use all the power sitting in GPUs to get near-instant update of a device when you change logic onscreen...

Outside of hobby use it wouldn't be too useful at all. Unlike incremental software compilation, changes made higher up in a design force structural changes all the way through the design, and changes in the lowest levels could be unfairly constrained by what is already in place. It is most likely that any reasonable commercial design will use over 50% of some of the resources on a chip (otherwise you would use a smaller chip) and that doesn't leave much room for rip-up and place and route.

You would also have the problem that the performance of your design will depend on everything that has happened to the design beforehand - so you can't give a copy of the source to a co-worker and expect them to get the same results.
No, I'm not talking incremental, I mean, you make a change to your HDL or whatever, and it recompiles, places, routes and downloads  in a second or two.
Quote

And I have to eat humble pie and say that Vivado isn't that bad (I didn't like it at first)
Is Vivado the new name for ISE, or something completely new?
If so what sort of differences are there?
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Offline c4757p

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #46 on: June 03, 2015, 11:01:40 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.

The archaic nature of the HDLs? What archaic nature would this be...?
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Offline hamster_nz

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #47 on: June 03, 2015, 11:10:21 pm »
Is Vivado the new name for ISE, or something completely new?
If so what sort of differences are there?

Vivado is the toolset for Xilinx's 7 series devices (Zynq, Aritx,...) . Much more oriented around building IP blocks with standard interfaces and joining them graphically to build your SoC or other design. It supports quite a high level of design automation (so when you add a GPIO IP block to your ARM SoC, it will connect up the AXI interconnects and insert any bridges and reset controllers you need and so on).

It also has support for high-level synthesis (i.e. a subset of C to HDL).

The tools are all quite integrated, so you can bounce between project, implemented design, RTL design, block-level design, simulation and hardware programming in the one application window. But you do have to drop out into Eclipse to do any S/W side of a design though.
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Offline Bassman59

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #48 on: June 03, 2015, 11:16:06 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.

The archaic nature of the HDLs? What archaic nature would this be...?

The fact that the two major HDLs were initially defined before some of these kids were born? You know, like how there are kids who want to do full-scale object-oriented coding on an 8051. Or something.

I have no idea. VHDL does everything I need it to do.
 

Online mikeselectricstuff

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Re: Lattice iCE40 Bitstream Reverse-Engineered
« Reply #49 on: June 03, 2015, 11:22:12 pm »
FPGA development environments are so universally awful that anything that can help spur innovation is a godsend.
No argument there, but IMO the biggest problem is the archaic nature of the HDLs, and definitely an area where something new is well overdue.

The archaic nature of the HDLs? What archaic nature would this be...?
Speaking about VHDL as that's what I sort-of know...
no block comments, no #define, #include, compile-time macros
Having to hope that the synthesis process infers what you want instead of being able to specify things more simply & directly (e.g. stuff like async resets).
Yet another different comment symbol
 No meaningful way (AFAICS) to easily manage build variants for different parts, pinouts etc. (more of an issue with the whole toolchain than the HDL) 

I'll admit I don't use FPGAs that often and don't know VHDL inside out, but it just seems that I'm often finding that the sort of things that I do routinely in software projects are a total ball-ache to do.

A concrete example - I use Lattice Diamond but my previous experience of ISE seemed pretty much the same.
I have a design that can be used on one of two different PCBs, with a few different FPGAs, depending on pins and memory required for a particular build.
It  already has a lot of paramaterization using VHDL constants ( much of which would have been easier with #ifdef type structures) , but what I'd like to be able to do is have a single #define in the top level source that would allow it to pull in the required set of pin definitions and define the FPGA type depending which PCB it will go on and how big a memory it needs.

And  there isn't even a way to have it automatically download to a device on a successful build. or even beep at me to tell me it's done compiling. Pathetic.



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