This is interesting, and relates to how the internal oscillators work.
If you look into the detail, the internal oscillators are actually trimable and on the FPGA I tested go from about 30MHz to 75MHz. Normally, the trim is loaded from OTP at power up, but if you tell iCECUBE that Vpp2V5 is connected to 1.8V (so the OTP is not available), it will connect the oscillator trim to the fabric and hard code it to a middling value instead. If you know what you're doing, you can also manually trim the oscillators (in Radiant or icestorm, but not iCEcube2).
Thus I suspect what is happening is the OTP is either corrupted or not being read correctly (could be QA failure, due to overheating from the rework, Vpp2V5 not being connected, or bad power-up cycles), so the trim values are stuck at all 1s so the oscillator is rammed to its maximum possible frequency, which is about 75MHz for the HFOSC (I haven't analysed the LFOSC in detail, but 16.49kHz sounds like a plausible maximum too).
If you're using iCEcube2, try setting the VPP_2V5_TO_1P8V attribute on the top level module as described on page 170 of the iCEcube2 user guide. This will hardcode the trim values to the midpoint, instead of trying to read them from OTP, and should get the oscillators within 10% at least.
The oscillators are officially specified to be within +/- 5%. Because of the trimming, at room temperature they should actually be considerably better than this, within 1% or so.