Setting log file to 'C:/Users/Detzler/Desktop/VHDL/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/standard.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package standard (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_1164.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package std_logic_1164 INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body std_logic_1164 (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mgc_qsim.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package qsim_logic INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body qsim_logic (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_bit.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package numeric_bit INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body numeric_bit (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_std.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package numeric_std INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body numeric_std (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/textio.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package textio INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_logic_textio.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package std_logic_textio INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body std_logic_textio (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_attr.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package attributes (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_misc.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package std_logic_misc INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body std_logic_misc INFO - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package math_real INFO - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body math_real (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package vl_types INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body vl_types (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_arit.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package std_logic_arith INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body std_logic_arith (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_sign.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package std_logic_signed INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body std_logic_signed (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_unsi.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package std_logic_unsigned INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body std_logic_unsigned (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/synattr.vhd INFO - C:/lscc/diamond/3.7_x64/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package attributes (VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.vhd (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/Top.vhd INFO - C:/Users/Detzler/Desktop/VHDL/Top.vhd(22,8-22,11) (VHDL-1012) analyzing entity top INFO - C:/Users/Detzler/Desktop/VHDL/Top.vhd(44,14-44,22) (VHDL-1010) analyzing architecture top_arch (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(14,8-14,19) (VHDL-1012) analyzing entity sicositable INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(24,14-24,23) (VHDL-1010) analyzing architecture structure (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/PISOshiftReg.vhd INFO - C:/Users/Detzler/Desktop/VHDL/PISOshiftReg.vhd(7,8-7,14) (VHDL-1012) analyzing entity pisosr INFO - C:/Users/Detzler/Desktop/VHDL/PISOshiftReg.vhd(20,14-20,25) (VHDL-1010) analyzing architecture pisosr_arch (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/Prescaler.vhd INFO - C:/Users/Detzler/Desktop/VHDL/Prescaler.vhd(7,8-7,17) (VHDL-1012) analyzing entity prescaler INFO - C:/Users/Detzler/Desktop/VHDL/Prescaler.vhd(17,14-17,28) (VHDL-1010) analyzing architecture prescaler_arch (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/Trigger.vhd INFO - C:/Users/Detzler/Desktop/VHDL/Trigger.vhd(7,8-7,15) (VHDL-1012) analyzing entity trigger INFO - C:/Users/Detzler/Desktop/VHDL/Trigger.vhd(18,14-18,26) (VHDL-1010) analyzing architecture trigger_arch (VHDL-1481) Analyzing VHDL file C:/Users/Detzler/Desktop/VHDL/PrescalerSCK.vhd INFO - C:/Users/Detzler/Desktop/VHDL/PrescalerSCK.vhd(7,8-7,20) (VHDL-1012) analyzing entity prescalersck INFO - C:/Users/Detzler/Desktop/VHDL/PrescalerSCK.vhd(17,14-17,31) (VHDL-1010) analyzing architecture prescalersck_arch INFO - C:/Users/Detzler/Desktop/VHDL/Top.vhd(22,8-22,11) (VHDL-1067) elaborating top(top_arch) INFO - C:/Users/Detzler/Desktop/VHDL/Top.vhd(130,2-136,4) (VHDL-1399) going to verilog side to elaborate module OSCH INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,8-1793,12) (VERI-1018) compiling module OSCH_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/Top.vhd(130,2-136,4) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(14,8-14,19) (VHDL-1067) elaborating SiCoSiTable_uniq_0(Structure) INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(403,5-404,59) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(403,5-404,59) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(406,5-407,59) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(406,5-407,59) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(409,5-410,59) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_3 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_3' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(409,5-410,59) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(412,5-413,59) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_4 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_4' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(412,5-413,59) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(415,5-416,59) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_5 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_5' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(415,5-416,59) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(418,5-419,55) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_6 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_6' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(418,5-419,55) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(421,5-422,68) (VHDL-1399) going to verilog side to elaborate module XOR2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1173,8-1173,12) (VERI-1018) compiling module XOR2_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1173,1-1177,10) (VERI-9000) elaborating module 'XOR2_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(421,5-422,68) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(424,5-425,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_7 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_7' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(424,5-425,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(427,5-428,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_8 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_8' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(427,5-428,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(430,5-431,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_9 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_9' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(430,5-431,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(433,5-434,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_10 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_10' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(433,5-434,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(436,5-437,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_11 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_11' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(436,5-437,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(439,5-440,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_12 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_12' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(439,5-440,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(442,5-443,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_13 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_13' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(442,5-443,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(445,5-446,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_14 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_14' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(445,5-446,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(448,5-449,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_15 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_15' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(448,5-449,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(451,5-452,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_16 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_16' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(451,5-452,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(454,5-455,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_17 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_17' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(454,5-455,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(457,5-458,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_18 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_18' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(457,5-458,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(460,5-461,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_19 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_19' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(460,5-461,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(463,5-464,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_20 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_20' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(463,5-464,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(466,5-467,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_21' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(466,5-467,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(469,5-470,47) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_22 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_22' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(469,5-470,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(472,5-473,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_23 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_23' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(472,5-473,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(475,5-476,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_24 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_24' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(475,5-476,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(478,5-479,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_25 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_25' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(478,5-479,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(481,5-482,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_26 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_26' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(481,5-482,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(484,5-485,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_27 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_27' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(484,5-485,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(487,5-488,53) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_28 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_28' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(487,5-488,53) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(490,5-491,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_29 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_29' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(490,5-491,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(493,5-494,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_30 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_30' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(493,5-494,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(496,5-497,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_31 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_31' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(496,5-497,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(499,5-500,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_32 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_32' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(499,5-500,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(502,5-503,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_33 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_33' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(502,5-503,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(505,5-506,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_34 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_34' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(505,5-506,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(508,5-509,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_35 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_35' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(508,5-509,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(511,5-512,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_36 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_36' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(511,5-512,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(514,5-515,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_37 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_37' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(514,5-515,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(517,5-518,47) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_38 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_38' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(517,5-518,47) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(520,5-523,72) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(520,5-523,72) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(525,5-528,63) (VHDL-1399) going to verilog side to elaborate module ROM16X1A INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,8-1051,16) (VERI-1018) compiling module ROM16X1A_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(525,5-528,63) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(530,5-531,45) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_39 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_39' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(530,5-531,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(533,5-534,51) (VHDL-1399) going to verilog side to elaborate module INV INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,8-563,11) (VERI-1018) compiling module INV_uniq_40 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_40' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(533,5-534,51) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(536,5-537,69) (VHDL-1399) going to verilog side to elaborate module AND2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,8-43,12) (VERI-1018) compiling module AND2_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(536,5-537,69) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(539,5-540,65) (VHDL-1399) going to verilog side to elaborate module AND2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,8-43,12) (VERI-1018) compiling module AND2_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(539,5-540,65) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(542,5-606,45) (VHDL-1399) going to verilog side to elaborate module DP8KC INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,8-1291,13) (VERI-1018) compiling module DP8KC_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(542,5-606,45) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(608,5-671,66) (VHDL-1399) going to verilog side to elaborate module DP8KC INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,8-1291,13) (VERI-1018) compiling module DP8KC_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(608,5-671,66) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(673,5-675,29) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(673,5-675,29) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(677,5-679,31) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(677,5-679,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(681,5-683,31) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_3 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(681,5-683,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(685,5-687,31) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_4 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(685,5-687,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(689,5-691,31) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_5 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(689,5-691,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(693,5-695,31) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_6 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(693,5-695,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(697,5-699,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_7 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(697,5-699,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(701,5-703,29) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_8 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(701,5-703,29) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(705,5-707,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(705,5-707,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(709,5-711,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(709,5-711,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(713,5-715,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_3 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_3' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(713,5-715,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(717,5-719,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_4 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_4' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(717,5-719,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(721,5-723,32) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_5 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_5' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(721,5-723,32) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(725,5-727,32) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_6 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_6' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(725,5-727,32) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(729,5-731,33) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_7 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_7' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(729,5-731,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(733,5-735,33) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_8 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_8' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(733,5-735,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(737,5-739,33) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_9 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_9' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(737,5-739,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(741,5-743,33) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_10 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_10' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(741,5-743,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(745,5-747,34) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_11 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_11' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(745,5-747,34) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(749,5-751,34) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_12 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_12' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(749,5-751,34) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(753,5-755,30) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_9 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(753,5-755,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(757,5-759,30) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_10 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(757,5-759,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(761,5-763,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_13 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_13' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(761,5-763,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(765,5-767,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_14 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_14' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(765,5-767,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(769,5-771,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_15 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_15' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(769,5-771,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(773,5-775,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_16 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_16' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(773,5-775,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(777,5-779,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_17 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_17' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(777,5-779,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(781,5-783,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_18 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_18' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(781,5-783,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(785,5-787,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_19 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_19' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(785,5-787,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(789,5-791,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_20 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_20' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(789,5-791,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(793,5-795,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_21' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(793,5-795,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(797,5-799,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_22 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_22' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(797,5-799,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(801,5-803,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_23 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_23' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(801,5-803,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(805,5-807,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_24 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_24' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(805,5-807,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(809,5-811,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_25 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_25' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(809,5-811,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(813,5-815,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_26 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_26' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(813,5-815,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(817,5-819,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_27 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_27' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(817,5-819,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(821,5-823,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_28 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_28' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(821,5-823,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(825,5-827,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_29 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_29' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(825,5-827,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(829,5-831,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_30 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_30' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(829,5-831,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(833,5-835,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_31 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_31' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(833,5-835,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(837,5-839,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_32 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_32' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(837,5-839,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(841,5-843,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_33 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_33' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(841,5-843,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(845,5-847,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_34 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_34' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(845,5-847,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(849,5-851,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_35 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_35' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(849,5-851,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(853,5-855,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_36 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_36' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(853,5-855,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(857,5-859,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_37 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_37' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(857,5-859,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(861,5-863,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_38 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_38' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(861,5-863,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(865,5-867,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_39 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_39' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(865,5-867,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(869,5-871,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_40 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_40' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(869,5-871,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(873,5-875,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_41 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_41' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(873,5-875,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(877,5-879,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_42 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_42' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(877,5-879,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(881,5-883,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_43 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_43' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(881,5-883,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(885,5-887,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_44 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_44' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(885,5-887,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(889,5-891,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_11 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(889,5-891,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(893,5-895,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_12 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(893,5-895,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(897,5-899,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_45 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_45' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(897,5-899,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(901,5-903,28) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_46 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_46' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(901,5-903,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(905,5-907,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_47 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_47' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(905,5-907,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(909,5-911,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_48 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_48' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(909,5-911,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(913,5-915,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_49 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_49' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(913,5-915,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(917,5-919,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_50 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_50' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(917,5-919,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(921,5-923,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_51 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_51' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(921,5-923,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(925,5-927,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_52 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_52' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(925,5-927,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(929,5-931,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_53 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_53' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(929,5-931,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(933,5-935,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_54 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_54' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(933,5-935,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(937,5-939,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_55 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_55' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(937,5-939,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(941,5-943,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_56 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_56' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(941,5-943,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(945,5-947,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_57 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_57' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(945,5-947,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(949,5-951,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_58 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_58' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(949,5-951,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(953,5-955,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_59 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_59' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(953,5-955,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(957,5-959,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_60 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_60' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(957,5-959,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(961,5-963,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_61 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_61' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(961,5-963,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(965,5-967,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_62 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_62' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(965,5-967,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(969,5-971,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_63 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_63' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(969,5-971,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(973,5-975,30) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_64 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_64' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(973,5-975,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(977,5-979,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_65 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_65' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(977,5-979,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(981,5-983,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_66 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_66' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(981,5-983,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(985,5-987,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_67 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_67' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(985,5-987,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(989,5-991,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_68 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_68' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(989,5-991,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(993,5-995,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_69 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_69' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(993,5-995,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(997,5-999,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_70 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_70' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(997,5-999,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1001,5-1003,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_71 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_71' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1001,5-1003,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1005,5-1007,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_72 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_72' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1005,5-1007,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1009,5-1011,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_73 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_73' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1009,5-1011,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1013,5-1015,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_74 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_74' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1013,5-1015,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1017,5-1019,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_75 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_75' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1017,5-1019,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1021,5-1023,31) (VHDL-1399) going to verilog side to elaborate module MUX21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,8-723,13) (VERI-1018) compiling module MUX21_uniq_76 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_76' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1021,5-1023,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1025,5-1027,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_13 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1025,5-1027,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1029,5-1031,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_14 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1029,5-1031,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1033,5-1035,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_15 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1033,5-1035,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1037,5-1039,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_16 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1037,5-1039,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1041,5-1043,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_17 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1041,5-1043,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1045,5-1047,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_18 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1045,5-1047,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1049,5-1051,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_19 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1049,5-1051,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1053,5-1055,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_20 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1053,5-1055,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1057,5-1059,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1057,5-1059,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1061,5-1063,25) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_22 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1061,5-1063,25) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1065,5-1067,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_23 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1065,5-1067,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1069,5-1071,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_24 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1069,5-1071,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1073,5-1075,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_25 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1073,5-1075,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1077,5-1079,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_26 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1077,5-1079,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1081,5-1083,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_27 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1081,5-1083,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1085,5-1087,26) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_28 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1085,5-1087,26) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1089,5-1091,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_29 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1089,5-1091,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1093,5-1095,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_30 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1093,5-1095,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1097,5-1099,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_31 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1097,5-1099,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1101,5-1103,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_32 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1101,5-1103,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1105,5-1107,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_33 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1105,5-1107,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1109,5-1111,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_34 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1109,5-1111,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1113,5-1115,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_35 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1113,5-1115,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1117,5-1119,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_36 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1117,5-1119,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1121,5-1123,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_37 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1121,5-1123,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1125,5-1127,27) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_38 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1125,5-1127,27) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1129,5-1131,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_39 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1129,5-1131,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1133,5-1135,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_40 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1133,5-1135,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1137,5-1139,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_41 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1137,5-1139,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1141,5-1143,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_42 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1141,5-1143,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1145,5-1147,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_43 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1145,5-1147,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1149,5-1151,28) (VHDL-1399) going to verilog side to elaborate module FD1P3DX INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,8-187,15) (VERI-1018) compiling module FD1P3DX_uniq_44 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1149,5-1151,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1153,5-1156,32) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1153,5-1156,32) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1158,5-1161,55) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_2 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_2' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1158,5-1161,55) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1163,5-1166,55) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_3 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_3' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1163,5-1166,55) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1168,5-1171,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_4 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_4' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1168,5-1171,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1173,5-1176,28) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_5 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_5' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1173,5-1176,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1178,5-1181,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_6 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_6' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1178,5-1181,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1183,5-1186,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_7 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_7' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1183,5-1186,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1188,5-1191,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_8 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_8' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1188,5-1191,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1193,5-1196,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_9 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_9' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1193,5-1196,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1198,5-1201,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_10 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_10' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1198,5-1201,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1203,5-1206,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_11 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_11' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1203,5-1206,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1208,5-1211,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_12 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_12' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1208,5-1211,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1213,5-1216,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_13 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_13' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1213,5-1216,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1218,5-1219,33) (VHDL-1399) going to verilog side to elaborate module VHI INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,8-1120,11) (VERI-1018) compiling module VHI_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1218,5-1219,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1221,5-1224,28) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_14 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_14' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1221,5-1224,28) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1226,5-1229,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_15 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_15' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1226,5-1229,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1231,5-1234,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_16 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_16' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1231,5-1234,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1236,5-1239,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_17 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_17' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1236,5-1239,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1241,5-1244,30) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_18 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_18' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1241,5-1244,30) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1246,5-1249,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_19 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_19' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1246,5-1249,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1251,5-1254,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_20 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_20' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1251,5-1254,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1256,5-1259,31) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_21 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_21' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1256,5-1259,31) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1261,5-1262,33) (VHDL-1399) going to verilog side to elaborate module VLO INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,8-1124,11) (VERI-1018) compiling module VLO_uniq_1 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1261,5-1262,33) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1264,5-1267,23) (VHDL-1399) going to verilog side to elaborate module FADD2B INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,8-138,14) (VERI-1018) compiling module FADD2B_uniq_22 INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_22' INFO - C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd(1264,5-1267,23) (VHDL-1400) back to vhdl to continue elaboration INFO - C:/Users/Detzler/Desktop/VHDL/PISOshiftReg.vhd(7,8-7,14) (VHDL-1067) elaborating PISOsr_uniq_0(PISOsr_arch) INFO - C:/Users/Detzler/Desktop/VHDL/Prescaler.vhd(7,8-7,17) (VHDL-1067) elaborating Prescaler_uniq_0(Prescaler_arch) INFO - C:/Users/Detzler/Desktop/VHDL/PrescalerSCK.vhd(7,8-7,20) (VHDL-1067) elaborating PrescalerSCK_uniq_0(PrescalerSCK_arch) INFO - C:/Users/Detzler/Desktop/VHDL/Trigger.vhd(7,8-7,15) (VHDL-1067) elaborating Trigger_uniq_0(Trigger_arch) INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_3' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_4' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_5' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_6' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1173,1-1177,10) (VERI-9000) elaborating module 'XOR2_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_7' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_8' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_9' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_10' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_11' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_12' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_13' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_14' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_15' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_16' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_17' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_18' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_19' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_20' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_21' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_22' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_23' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_24' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_25' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_26' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_27' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_28' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_29' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_30' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_31' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_32' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_33' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_34' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_35' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_36' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_37' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_38' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1051,1-1060,10) (VERI-9000) elaborating module 'ROM16X1A_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_39' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(563,1-566,10) (VERI-9000) elaborating module 'INV_uniq_40' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43,1-47,10) (VERI-9000) elaborating module 'AND2_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_3' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_4' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_5' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_6' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_7' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_8' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_3' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_4' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_5' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_6' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_7' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_8' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_9' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_10' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_11' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_12' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_9' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_10' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_13' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_14' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_15' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_16' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_17' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_18' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_19' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_20' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_21' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_22' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_23' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_24' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_25' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_26' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_27' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_28' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_29' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_30' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_31' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_32' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_33' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_34' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_35' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_36' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_37' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_38' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_39' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_40' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_41' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_42' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_43' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_44' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_11' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_12' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_45' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_46' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_47' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_48' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_49' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_50' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_51' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_52' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_53' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_54' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_55' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_56' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_57' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_58' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_59' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_60' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_61' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_62' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_63' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_64' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_65' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_66' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_67' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_68' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_69' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_70' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_71' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_72' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_73' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_74' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_75' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(723,1-729,10) (VERI-9000) elaborating module 'MUX21_uniq_76' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_13' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_14' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_15' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_16' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_17' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_18' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_19' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_20' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_21' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_22' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_23' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_24' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_25' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_26' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_27' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_28' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_29' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_30' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_31' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_32' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_33' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_34' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_35' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_36' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_37' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_38' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_39' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_40' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_41' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_42' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_43' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187,1-196,10) (VERI-9000) elaborating module 'FD1P3DX_uniq_44' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_2' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_3' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_4' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_5' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_6' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_7' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_8' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_9' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_10' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_11' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_12' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_13' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_14' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_15' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_16' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_17' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_18' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_19' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_20' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_21' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138,1-142,10) (VERI-9000) elaborating module 'FADD2B_uniq_22' Done: design load finished with (0) errors, and (0) warnings