Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Thu Apr 19 09:44:30 2018

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 1000.000000 -name clk1 [get_nets TP1_c]
            3 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 991.342ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \i_Trigger/cmd_21  (from TP1_c +)
   Destination:    FD1P3AX    SP             \i_PISOsr/dout_92  (to TP1_c +)

   Delay:                   8.125ns  (21.6% logic, 78.4% route), 2 logic levels.

 Constraint Details:

      8.125ns data_path \i_Trigger/cmd_21 to \i_PISOsr/dout_92 meets
    1000.000ns delay constraint less
      0.533ns LCE_S requirement (totaling 999.467ns) by 991.342ns

 Path Details: \i_Trigger/cmd_21 to \i_PISOsr/dout_92

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/cmd_21 (from TP1_c)
Route         3   e 3.259                                  D1_c
LUT4        ---     0.922              A to Z              \i_Trigger/i77_1_lut
Route         3   e 3.115                                  TP1_c_enable_2
                  --------
                    8.125  (21.6% logic, 78.4% route), 2 logic levels.


Passed:  The following path meets requirements by 991.342ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \i_Trigger/cmd_21  (from TP1_c +)
   Destination:    FD1P3AX    SP             \i_PISOsr/empty_91  (to TP1_c +)

   Delay:                   8.125ns  (21.6% logic, 78.4% route), 2 logic levels.

 Constraint Details:

      8.125ns data_path \i_Trigger/cmd_21 to \i_PISOsr/empty_91 meets
    1000.000ns delay constraint less
      0.533ns LCE_S requirement (totaling 999.467ns) by 991.342ns

 Path Details: \i_Trigger/cmd_21 to \i_PISOsr/empty_91

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/cmd_21 (from TP1_c)
Route         3   e 3.259                                  D1_c
LUT4        ---     0.922              A to Z              \i_Trigger/i77_1_lut
Route         3   e 3.115                                  TP1_c_enable_2
                  --------
                    8.125  (21.6% logic, 78.4% route), 2 logic levels.


Passed:  The following path meets requirements by 992.366ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             \i_Trigger/cmd_21  (from TP1_c +)
   Destination:    FD1P3AX    D              \i_PISOsr/dout_92  (to TP1_c +)

   Delay:                   7.334ns  (23.9% logic, 76.1% route), 2 logic levels.

 Constraint Details:

      7.334ns data_path \i_Trigger/cmd_21 to \i_PISOsr/dout_92 meets
    1000.000ns delay constraint less
      0.300ns L_S requirement (totaling 999.700ns) by 992.366ns

 Path Details: \i_Trigger/cmd_21 to \i_PISOsr/dout_92

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/cmd_21 (from TP1_c)
Route         3   e 3.259                                  D1_c
LUT4        ---     0.922              C to Z              \i_PISOsr/i325_3_lut
Route         1   e 2.324                                  \i_PISOsr/n190
                  --------
                    7.334  (23.9% logic, 76.1% route), 2 logic levels.

Report: 8.658 ns is the maximum delay for this constraint.



================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets TP2_c]
            1612 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 978.765ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \i_Trigger/Trigger.debounce_i0_i4  (from TP2_c +)
   Destination:    FD1P3AX    D              \i_Trigger/Trigger.debounce_i0_i6  (to TP2_c +)

   Delay:                  20.935ns  (31.3% logic, 68.7% route), 7 logic levels.

 Constraint Details:

     20.935ns data_path \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i6 meets
    1000.000ns delay constraint less
      0.300ns L_S requirement (totaling 999.700ns) by 978.765ns

 Path Details: \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i6

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/Trigger.debounce_i0_i4 (from TP2_c)
Route         2   e 2.967                                  \i_Trigger/Trigger.debounce[4]
LUT4        ---     0.922              C to Z              \i_Trigger/i432_3_lut
Route         3   e 3.115                                  \i_Trigger/n545
LUT4        ---     0.922              A to Z              \i_Trigger/i1_2_lut_rep_6_4_lut
Route         1   e 2.324                                  \i_Trigger/n601
LUT4        ---     0.922              C to Z              \i_Trigger/i1_4_lut
Route         6   e 3.614                                  \i_Trigger/n244
A1_TO_FCO   ---     1.545           B[2] to COUT           \i_Trigger/add_73_3
Route         1   e 0.020                                  \i_Trigger/n475
FCI_TO_FCO  ---     0.293            CIN to COUT           \i_Trigger/add_73_5
Route         1   e 0.020                                  \i_Trigger/n476
FCI_TO_F    ---     1.118            CIN to S[2]           \i_Trigger/add_73_7
Route         1   e 2.324                                  \i_Trigger/Trigger.debounce_6__N_161[6]
                  --------
                   20.935  (31.3% logic, 68.7% route), 7 logic levels.


Passed:  The following path meets requirements by 978.765ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \i_Trigger/Trigger.debounce_i0_i4  (from TP2_c +)
   Destination:    FD1P3AX    D              \i_Trigger/Trigger.debounce_i0_i6  (to TP2_c +)

   Delay:                  20.935ns  (31.3% logic, 68.7% route), 7 logic levels.

 Constraint Details:

     20.935ns data_path \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i6 meets
    1000.000ns delay constraint less
      0.300ns L_S requirement (totaling 999.700ns) by 978.765ns

 Path Details: \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i6

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/Trigger.debounce_i0_i4 (from TP2_c)
Route         2   e 2.967                                  \i_Trigger/Trigger.debounce[4]
LUT4        ---     0.922              C to Z              \i_Trigger/i432_3_lut
Route         3   e 3.115                                  \i_Trigger/n545
LUT4        ---     0.922              A to Z              \i_Trigger/i1_2_lut_rep_6_4_lut
Route         1   e 2.324                                  \i_Trigger/n601
LUT4        ---     0.922              C to Z              \i_Trigger/i1_4_lut
Route         6   e 3.614                                  \i_Trigger/n244
A1_TO_FCO   ---     1.545           B[2] to COUT           \i_Trigger/add_73_3
Route         1   e 0.020                                  \i_Trigger/n475
FCI_TO_FCO  ---     0.293            CIN to COUT           \i_Trigger/add_73_5
Route         1   e 0.020                                  \i_Trigger/n476
FCI_TO_F    ---     1.118            CIN to S[2]           \i_Trigger/add_73_7
Route         1   e 2.324                                  \i_Trigger/Trigger.debounce_6__N_161[6]
                  --------
                   20.935  (31.3% logic, 68.7% route), 7 logic levels.


Passed:  The following path meets requirements by 978.765ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \i_Trigger/Trigger.debounce_i0_i4  (from TP2_c +)
   Destination:    FD1P3AX    D              \i_Trigger/Trigger.debounce_i0_i5  (to TP2_c +)

   Delay:                  20.935ns  (31.3% logic, 68.7% route), 7 logic levels.

 Constraint Details:

     20.935ns data_path \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i5 meets
    1000.000ns delay constraint less
      0.300ns L_S requirement (totaling 999.700ns) by 978.765ns

 Path Details: \i_Trigger/Trigger.debounce_i0_i4 to \i_Trigger/Trigger.debounce_i0_i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.829             CK to Q              \i_Trigger/Trigger.debounce_i0_i4 (from TP2_c)
Route         2   e 2.967                                  \i_Trigger/Trigger.debounce[4]
LUT4        ---     0.922              C to Z              \i_Trigger/i432_3_lut
Route         3   e 3.115                                  \i_Trigger/n545
LUT4        ---     0.922              A to Z              \i_Trigger/i1_2_lut_rep_6_4_lut
Route         1   e 2.324                                  \i_Trigger/n601
LUT4        ---     0.922              C to Z              \i_Trigger/i1_4_lut
Route         6   e 3.614                                  \i_Trigger/n244
A1_TO_FCO   ---     1.545           B[2] to COUT           \i_Trigger/add_73_3
Route         1   e 0.020                                  \i_Trigger/n475
FCI_TO_FCO  ---     0.293            CIN to COUT           \i_Trigger/add_73_5
Route         1   e 0.020                                  \i_Trigger/n476
FCI_TO_F    ---     1.118            CIN to S[2]           \i_Trigger/add_73_7
Route         1   e 2.324                                  \i_Trigger/Trigger.debounce_6__N_161[5]
                  --------
                   20.935  (31.3% logic, 68.7% route), 7 logic levels.

Report: 21.235 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk1 [get_nets TP1_c]                   |  1000.000 ns|     8.658 ns|     2  
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets TP2_c]                   |  1000.000 ns|    21.235 ns|     7  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  1615 paths, 107 nets, and 286 connections (92.6% coverage)


Peak memory: 74285056 bytes, TRCE: 1777664 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs