Lattice Mapping Report File for Design Module 'top' Design Information Command line: map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Commercial BreakoutBoard_impl1.ngd -o BreakoutBoard_impl1_map.ncd -pr BreakoutBoard_impl1.prf -mp BreakoutBoard_impl1.mrp -lpf C:/Users/Detzler/Documents/BusPirate/impl1/BreakoutBoard_impl1.lpf -lpf C:/Users/Detzler/Documents/BusPirate/BreakoutBoard.lpf -c 0 -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-1200ZETQFP144 Target Performance: 1 Mapper: xo2c00, version: Diamond (64-bit) 3.7.0.96.1 Mapped on: 04/19/18 09:14:32 Design Summary Number of registers: 51 out of 1604 (3%) PFU registers: 51 out of 1280 (4%) PIO registers: 0 out of 324 (0%) Number of SLICEs: 30 out of 640 (5%) SLICEs as Logic/ROM: 30 out of 640 (5%) SLICEs as RAM: 0 out of 480 (0%) SLICEs as Carry: 10 out of 640 (2%) Number of LUT4s: 56 out of 1280 (4%) Number used as logic LUTs: 36 Number used as distributed RAM: 0 Number used as ripple logic: 20 Number used as shift registers: 0 Number of PIO sites used: 15 + 4(JTAG) out of 108 (18%) Number of block RAMs: 0 out of 7 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : Yes Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 1 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 2 Net TP2_c: 27 loads, 27 rising, 0 falling (Driver: OSC_inst ) Net TP1_c: 3 loads, 3 rising, 0 falling (Driver: i_Prescaler/Prescaler.outx_15 ) Number of Clock Enables: 3 Net TP2_c_enable_36: 13 loads, 13 LSLICEs Net D1_c: 2 loads, 2 LSLICEs Net TP2_c_enable_12: 6 loads, 6 LSLICEs Number of LSRs: 2 Net n290: 6 loads, 6 LSLICEs Net i_PrescalerSCK/n289: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net TP2_c_enable_36: 13 loads Net n290: 10 loads Net i_Trigger/n244: 6 loads Net i_Trigger/Trigger.debounce_0: 6 loads Net i_Trigger/Trigger.debounce_1: 6 loads Net i_Trigger/Trigger.debounce_2: 6 loads Net TP2_c_enable_12: 6 loads Net D1_c: 5 loads Net i_PrescalerSCK/PrescalerSCK.counter_0: 5 loads Net VCC_net: 5 loads Number of warnings: 0 Number of errors: 0 Design Errors/Warnings No errors or warnings present. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | D2 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D3 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D1 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D4 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D5 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D6 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D7 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | D8 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | SCL | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | SOut | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | Sync | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | TP1 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | TP2 | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | TasterA | INPUT | LVCMOS12 | | +---------------------+-----------+-----------+------------+ | TasterB | INPUT | LVCMOS12 | | +---------------------+-----------+-----------+------------+ Removed logic Signal TP1_c_enable_2 was merged into signal D1_c Signal GND_net undriven or does not drive anything - clipped. Signal n631 undriven or does not drive anything - clipped. Signal i_Prescaler/Prescaler.counter_74_add_4_11/S1 undriven or does not drive anything - clipped. Signal i_Prescaler/Prescaler.counter_74_add_4_11/CO undriven or does not drive anything - clipped. Signal i_Prescaler/Prescaler.counter_74_add_4_1/S0 undriven or does not drive anything - clipped. Signal i_Prescaler/Prescaler.counter_74_add_4_1/CI undriven or does not drive anything - clipped. Signal i_Trigger/add_73_7/CO undriven or does not drive anything - clipped. Signal i_Trigger/add_73_1/S0 undriven or does not drive anything - clipped. Signal i_Trigger/add_73_1/CI undriven or does not drive anything - clipped. Block i_Trigger/i77_1_lut was optimized away. Block i1 was optimized away. Block m0_lut was optimized away. Memory Usage OSC Summary ----------- OSC 1: Pin/Node Value OSC Instance Name: OSC_inst OSC Type: OSCH STDBY Input: NONE OSC Output: PIN,NODE TP2_c OSC Nominal Frequency (MHz): 2.08 ASIC Components --------------- Instance Name: OSC_inst Type: OSCH GSR Usage --------- GSR Component: The Global Set Reset (GSR) resource has been used to implement a global reset of the design. The reset signal used for GSR control is 'D1_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components with disabled GSR Property ------------------------------------- These components have the GSR property set to DISABLED. The components will not respond to the reset signal 'D1_c' via the GSR component. Type and number of components of the type: Register = 26 Type and instance name of component: Register : i_Trigger/Trigger.debounce_i0_i0 Register : i_Trigger/Trigger.debounce_i0_i6 Register : i_Trigger/Trigger.debounce_i0_i5 Register : i_Trigger/Trigger.debounce_i0_i4 Register : i_Trigger/Trigger.debounce_i0_i3 Register : i_Trigger/Trigger.debounce_i0_i2 Register : i_Trigger/cmd_21 Register : i_Trigger/Trigger.debounce_i0_i1 Register : i_PrescalerSCK/PrescalerSCK.counter_75__i0 Register : i_PrescalerSCK/PrescalerSCK.counter_75__i1 Register : i_PrescalerSCK/PrescalerSCK.counter_75__i2 Register : i_PrescalerSCK/PrescalerSCK.outx_15 Register : i_PrescalerSCK/PrescalerSCK.counter_75__i3 Register : i_PISOsr/dout_92 Register : i_PISOsr/empty_91 Register : i_Prescaler/Prescaler.counter_74__i2 Register : i_Prescaler/Prescaler.counter_74__i1 Register : i_Prescaler/Prescaler.counter_74__i0 Register : i_Prescaler/Prescaler.outx_15 Register : i_Prescaler/Prescaler.counter_74__i9 Register : i_Prescaler/Prescaler.counter_74__i8 Register : i_Prescaler/Prescaler.counter_74__i7 Register : i_Prescaler/Prescaler.counter_74__i6 Register : i_Prescaler/Prescaler.counter_74__i5 Register : i_Prescaler/Prescaler.counter_74__i4 Register : i_Prescaler/Prescaler.counter_74__i3 Run Time and Memory Usage ------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 38 MB Copyright (c) 1991-1994 by NeoCAD Inc. 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