Synthesis Report
#Build: Synplify Pro K-2015.09L-2, Build 126R, Dec 14 2015
#install: C:\lscc\diamond\3.7_x64\synpbase
#OS: Windows 7 6.1
#Hostname: PC-DETZLER

# Wed Apr 18 12:25:37 2018

#Implementation: impl1

Synopsys HDL Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys VHDL Compiler, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N: CD720 :"C:\lscc\diamond\3.7_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Users\Detzler\Documents\BusPirate\Top.vhd":22:7:22:9|Top entity is set to top.
VHDL syntax check successful!
@N: CD630 :"C:\Users\Detzler\Documents\BusPirate\Top.vhd":22:7:22:9|Synthesizing work.top.top_arch.
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":2291:10:2291:13|Synthesizing work.osch.syn_black_box.
Post processing for work.osch.syn_black_box
@N: CD630 :"C:\Users\Detzler\Documents\BusPirate\Trigger.vhd":7:7:7:13|Synthesizing work.trigger.trigger_arch.
Post processing for work.trigger.trigger_arch
@N: CD630 :"C:\Users\Detzler\Documents\BusPirate\Prescaler.vhd":7:7:7:15|Synthesizing work.prescaler.prescaler_arch.
Post processing for work.prescaler.prescaler_arch
@N: CD630 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":7:7:7:12|Synthesizing work.pisosr.pisosr_arch.
@W: CD434 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":26:27:26:32|Signal enable in the sensitivity list is not used in the process
@W: CD434 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":26:42:26:46|Signal reset in the sensitivity list is not used in the process
@W: CG296 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":26:10:26:16|Incomplete sensitivity list - assuming completeness
@W: CG290 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":30:38:30:40|Referenced variable din is not in sensitivity list
Post processing for work.pisosr.pisosr_arch
@A: CL282 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":29:2:29:3|Feedback mux created for signal dout -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CD630 :"C:\Users\Detzler\Documents\BusPirate\SiCoSiTable.vhd":14:7:14:17|Synthesizing work.sicositable.structure.
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1407:10:1407:17|Synthesizing work.rom16x1a.syn_black_box.
Post processing for work.rom16x1a.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1699:10:1699:14|Synthesizing work.dp8kc.syn_black_box.
Post processing for work.dp8kc.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":234:10:234:16|Synthesizing work.fd1p3dx.syn_black_box.
Post processing for work.fd1p3dx.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":177:10:177:15|Synthesizing work.fadd2b.syn_black_box.
Post processing for work.fadd2b.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1490:10:1490:12|Synthesizing work.vlo.syn_black_box.
Post processing for work.vlo.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1483:10:1483:12|Synthesizing work.vhi.syn_black_box.
Post processing for work.vhi.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1013:10:1013:14|Synthesizing work.mux21.syn_black_box.
Post processing for work.mux21.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":64:10:64:13|Synthesizing work.and2.syn_black_box.
Post processing for work.and2.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":681:10:681:12|Synthesizing work.inv.syn_black_box.
Post processing for work.inv.syn_black_box
@N: CD630 :"C:\lscc\diamond\3.7_x64\cae_library\synthesis\vhdl\machxo2.vhd":1497:10:1497:13|Synthesizing work.xor2.syn_black_box.
Post processing for work.xor2.syn_black_box
Post processing for work.sicositable.structure
Post processing for work.top.top_arch
@N: CL159 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":13:1:13:6|Input enable is unused.
@N: CL159 :"C:\Users\Detzler\Documents\BusPirate\PISOshiftReg.vhd":16:1:16:5|Input reset is unused.

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Apr 18 12:25:37 2018

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Apr 18 12:25:38 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Apr 18 12:25:38 2018

###########################################################]
Synopsys Netlist Linker, version comp201509p1, Build 145R, built Dec  9 2015
@N|Running in 64-bit mode

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Apr 18 12:25:39 2018

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@L: C:\Users\Detzler\Documents\BusPirate\impl1\BreakoutBoard_impl1_scck.rpt 
Printing clock  summary report in "C:\Users\Detzler\Documents\BusPirate\impl1\BreakoutBoard_impl1_scck.rpt" file 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@A: FX681 :"c:\users\detzler\documents\buspirate\trigger.vhd":27:1:27:2|Initial value on register debounce[6:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1089:4:1089:8|Removing sequential instance FF_15 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1093:4:1093:8|Removing sequential instance FF_14 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1097:4:1097:8|Removing sequential instance FF_13 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1101:4:1101:8|Removing sequential instance FF_12 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1105:4:1105:8|Removing sequential instance FF_11 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1109:4:1109:8|Removing sequential instance FF_10 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1113:4:1113:7|Removing sequential instance FF_9 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1117:4:1117:7|Removing sequential instance FF_8 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1121:4:1121:7|Removing sequential instance FF_7 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1125:4:1125:7|Removing sequential instance FF_6 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1129:4:1129:7|Removing sequential instance FF_5 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1133:4:1133:7|Removing sequential instance FF_4 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1137:4:1137:7|Removing sequential instance FF_3 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1141:4:1141:7|Removing sequential instance FF_2 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1145:4:1145:7|Removing sequential instance FF_1 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":1149:4:1149:7|Removing sequential instance FF_0 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":889:4:889:8|Removing sequential instance FF_33 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
@N: BN362 :"c:\users\detzler\documents\buspirate\sicositable.vhd":753:4:753:8|Removing sequential instance FF_35 (in view: work.SiCoSiTable(structure)) of type view:LUCENT.FD1P3DX(PRIM) because it does not drive other instances.
ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=7  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



Clock Summary
*****************

Start                              Requested     Requested     Clock                                         Clock              
Clock                              Frequency     Period        Type                                          Group              
--------------------------------------------------------------------------------------------------------------------------------
PISOsr|empty_derived_clock         2.1 MHz       480.769       derived (from top|osc_clk_inferred_clock)     Inferred_clkgroup_0
Prescaler|clkout_derived_clock     2.1 MHz       480.769       derived (from top|osc_clk_inferred_clock)     Inferred_clkgroup_0
System                             1.0 MHz       1000.000      system                                        system_clkgroup    
top|osc_clk_inferred_clock         2.1 MHz       480.769       inferred                                      Inferred_clkgroup_0
================================================================================================================================

@W: MT529 :"c:\users\detzler\documents\buspirate\prescaler.vhd":28:1:28:2|Found inferred clock top|osc_clk_inferred_clock which controls 11 sequential elements including i_Prescaler.counter[9:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Finished Pre Mapping Phase.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

None
None

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Apr 18 12:25:39 2018

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1368R, Built Jan  8 2016 09:37:50
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version K-2015.09L-2

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Available hyper_sources - for debug and ip models
	None Found

@N: FX493 |Applying initial value "0000000" on instance i_Trigger.debounce[6:0] 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		   470.75ns		  65 /        46

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB)

@N: MT611 :|Automatically generated clock Prescaler|clkout_derived_clock is not used and is being removed


@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
18 gated/generated clock tree(s) driving 108 clock pin(s) of sequential element(s)
0 instances converted, 108 sequential instances remain driven by gated/generated clocks

============================================================================================================ Gated/Generated Clocks =============================================================================================================
Clock Tree ID     Driving Element         Drive Element Type     Fanout     Sample Instance                        Explanation                                                                                                                   
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
@K:CKID0001       OSC_inst                OSCH                   62         i_Trigger.cmd                          Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements
@K:CKID0002       i_PISOsr.empty          FD1P3AX                30         i_SiCoSiTable.FF_16                    No gated clock conversion method for cell cell:LUCENT.FD1P3DX                                                                 
@K:CKID0003       i_PISOsr.un1_din_47     ORCALUT4               1          i_PISOsr.data_register_1_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0004       i_PISOsr.un1_din_42     ORCALUT4               1          i_PISOsr.data_register_6_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0005       i_PISOsr.un1_din_43     ORCALUT4               1          i_PISOsr.data_register_5_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0006       i_PISOsr.un1_din_44     ORCALUT4               1          i_PISOsr.data_register_4_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0007       i_PISOsr.un1_din_45     ORCALUT4               1          i_PISOsr.data_register_3_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0008       i_PISOsr.un1_din_46     ORCALUT4               1          i_PISOsr.data_register_2_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0009       i_PISOsr.un1_din_37     ORCALUT4               1          i_PISOsr.data_register_11_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0010       i_PISOsr.un1_din_38     ORCALUT4               1          i_PISOsr.data_register_10_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0011       i_PISOsr.un1_din_39     ORCALUT4               1          i_PISOsr.data_register_9_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0012       i_PISOsr.un1_din_40     ORCALUT4               1          i_PISOsr.data_register_8_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0013       i_PISOsr.un1_din_41     ORCALUT4               1          i_PISOsr.data_register_7_.res_lat      Unconverted clock gate                                                                                                        
@K:CKID0014       i_PISOsr.un1_din_32     ORCALUT4               1          i_PISOsr.data_register_16_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0015       i_PISOsr.un1_din_33     ORCALUT4               1          i_PISOsr.data_register_15_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0016       i_PISOsr.un1_din_34     ORCALUT4               1          i_PISOsr.data_register_14_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0017       i_PISOsr.un1_din_35     ORCALUT4               1          i_PISOsr.data_register_13_.res_lat     Unconverted clock gate                                                                                                        
@K:CKID0018       i_PISOsr.un1_din_36     ORCALUT4               1          i_PISOsr.data_register_12_.res_lat     Unconverted clock gate                                                                                                        
=================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 140MB)

Writing Analyst data base C:\Users\Detzler\Documents\BusPirate\impl1\synwork\BreakoutBoard_impl1_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB)

Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Users\Detzler\Documents\BusPirate\impl1\BreakoutBoard_impl1.edi
K-2015.09L-2
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)


Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB)

@W: MT420 |Found inferred clock top|osc_clk_inferred_clock with period 480.77ns. Please declare a user-defined clock on object "n:osc_clk"
@N: MT615 |Found clock PISOsr|empty_derived_clock with period 480.77ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Apr 18 12:25:40 2018
#


Top view:               top
Requested Frequency:    2.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary
*******************


Worst slack in design: 470.755

                               Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock                 Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------
PISOsr|empty_derived_clock     2.1 MHz       319.4 MHz     480.769       3.131         960.461     derived      Inferred_clkgroup_0
top|osc_clk_inferred_clock     2.1 MHz       116.2 MHz     480.769       8.606         472.163     inferred     Inferred_clkgroup_0
System                         1.0 MHz       384.4 MHz     1000.000      2.602         997.398     system       system_clkgroup    
===================================================================================================================================





Clock Relationships
*******************

Clocks                                                  |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------------
System                      System                      |  1000.000    997.398  |  No paths    -      |  No paths    -      |  No paths    -    
System                      top|osc_clk_inferred_clock  |  480.769     476.083  |  No paths    -      |  No paths    -      |  No paths    -    
System                      PISOsr|empty_derived_clock  |  480.769     479.087  |  No paths    -      |  No paths    -      |  No paths    -    
top|osc_clk_inferred_clock  top|osc_clk_inferred_clock  |  480.769     472.163  |  No paths    -      |  No paths    -      |  No paths    -    
top|osc_clk_inferred_clock  PISOsr|empty_derived_clock  |  480.769     477.639  |  No paths    -      |  No paths    -      |  No paths    -    
PISOsr|empty_derived_clock  System                      |  480.769     470.755  |  No paths    -      |  No paths    -      |  No paths    -    
PISOsr|empty_derived_clock  PISOsr|empty_derived_clock  |  480.769     960.461  |  No paths    -      |  No paths    -      |  No paths    -    
================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: PISOsr|empty_derived_clock
====================================



Starting Points with Worst Slack
********************************

                                  Starting                                                        Arrival            
Instance                          Reference                      Type      Pin      Net           Time        Slack  
                                  Clock                                                                              
---------------------------------------------------------------------------------------------------------------------
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB0     rom_dob       5.353       470.755
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB1     rom_dob_1     5.353       471.466
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB2     rom_dob_2     5.353       471.466
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB3     rom_dob_3     5.353       471.608
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB4     rom_dob_4     5.353       471.608
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB5     rom_dob_5     5.353       471.751
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB6     rom_dob_6     5.353       471.751
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB7     rom_dob_7     5.353       471.894
i_SiCoSiTable.triglut_1_0_0_1     PISOsr|empty_derived_clock     DP8KC     DOB8     rom_dob_8     5.353       471.894
i_SiCoSiTable.triglut_1_0_1_0     PISOsr|empty_derived_clock     DP8KC     DOB0     rom_dob_9     5.353       472.037
=====================================================================================================================


Ending Points with Worst Slack
******************************

                          Starting                                                          Required            
Instance                  Reference                      Type      Pin     Net              Time         Slack  
                          Clock                                                                                 
----------------------------------------------------------------------------------------------------------------
i_SiCoSiTable.muxb_48     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_15     480.769      470.755
i_SiCoSiTable.muxb_49     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_14     480.769      470.898
i_SiCoSiTable.muxb_50     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_13     480.769      470.898
i_SiCoSiTable.muxb_51     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_12     480.769      471.041
i_SiCoSiTable.muxb_52     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_11     480.769      471.041
i_SiCoSiTable.muxb_53     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_10     480.769      471.183
i_SiCoSiTable.muxb_54     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_9      480.769      471.183
i_SiCoSiTable.muxb_55     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_8      480.769      471.326
i_SiCoSiTable.muxb_56     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_7      480.769      471.326
i_SiCoSiTable.muxb_57     PISOsr|empty_derived_clock     MUX21     D1      rom_dob_n_6      480.769      471.469
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         480.769

    - Propagation time:                      10.014
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     470.755

    Number of logic level(s):                10
    Starting point:                          i_SiCoSiTable.triglut_1_0_0_1 / DOB0
    Ending point:                            i_SiCoSiTable.muxb_48 / D1
    The start point is clocked by            PISOsr|empty_derived_clock [rising] on pin CLKB
    The end   point is clocked by            System [rising]

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                              Type       Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
i_SiCoSiTable.triglut_1_0_0_1     DP8KC      DOB0     Out     5.353     5.353       -         
rom_dob                           Net        -        -       -         -           2         
i_SiCoSiTable.INV_2               INV        A        In      0.000     5.353       -         
i_SiCoSiTable.INV_2               INV        Z        Out     0.568     5.921       -         
rom_dob_inv                       Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_0     FADD2B     A1       In      0.000     5.921       -         
i_SiCoSiTable.neg_rom_dob_n_0     FADD2B     COUT     Out     1.545     7.466       -         
co0_2                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_1     FSUB2B     BI       In      0.000     7.466       -         
i_SiCoSiTable.neg_rom_dob_n_1     FSUB2B     BOUT     Out     0.143     7.609       -         
co1_2                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_2     FSUB2B     BI       In      0.000     7.609       -         
i_SiCoSiTable.neg_rom_dob_n_2     FSUB2B     BOUT     Out     0.143     7.751       -         
co2_2                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_3     FSUB2B     BI       In      0.000     7.751       -         
i_SiCoSiTable.neg_rom_dob_n_3     FSUB2B     BOUT     Out     0.143     7.894       -         
co3_1                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_4     FSUB2B     BI       In      0.000     7.894       -         
i_SiCoSiTable.neg_rom_dob_n_4     FSUB2B     BOUT     Out     0.143     8.037       -         
co4_1                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_5     FSUB2B     BI       In      0.000     8.037       -         
i_SiCoSiTable.neg_rom_dob_n_5     FSUB2B     BOUT     Out     0.143     8.180       -         
co5_1                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_6     FSUB2B     BI       In      0.000     8.180       -         
i_SiCoSiTable.neg_rom_dob_n_6     FSUB2B     BOUT     Out     0.143     8.322       -         
co6_1                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_7     FSUB2B     BI       In      0.000     8.322       -         
i_SiCoSiTable.neg_rom_dob_n_7     FSUB2B     BOUT     Out     0.143     8.465       -         
co7_1                             Net        -        -       -         -           1         
i_SiCoSiTable.neg_rom_dob_n_8     FADD2B     CI       In      0.000     8.465       -         
i_SiCoSiTable.neg_rom_dob_n_8     FADD2B     S0       Out     1.549     10.014      -         
rom_dob_n_15                      Net        -        -       -         -           1         
i_SiCoSiTable.muxb_48             MUX21      D1       In      0.000     10.014      -         
==============================================================================================




====================================
Detailed Report for Clock: top|osc_clk_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                           Starting                                                           Arrival            
Instance                   Reference                      Type        Pin     Net             Time        Slack  
                           Clock                                                                                 
-----------------------------------------------------------------------------------------------------------------
i_Prescaler.counter[0]     top|osc_clk_inferred_clock     FD1S3AX     Q       counter[0]      1.108       472.163
i_Prescaler.counter[1]     top|osc_clk_inferred_clock     FD1S3AX     Q       counter[1]      0.972       472.442
i_Prescaler.counter[2]     top|osc_clk_inferred_clock     FD1S3AX     Q       counter[2]      0.972       472.442
i_Prescaler.counter[3]     top|osc_clk_inferred_clock     FD1S3IX     Q       counter[3]      0.972       472.585
i_Prescaler.counter[4]     top|osc_clk_inferred_clock     FD1S3AX     Q       counter[4]      0.972       472.585
i_Prescaler.counter[5]     top|osc_clk_inferred_clock     FD1S3IX     Q       counter[5]      0.972       472.728
i_Prescaler.counter[6]     top|osc_clk_inferred_clock     FD1S3IX     Q       counter[6]      0.972       472.728
i_Trigger.debounce[3]      top|osc_clk_inferred_clock     FD1P3AX     Q       debounce[3]     1.108       473.649
i_Trigger.debounce[4]      top|osc_clk_inferred_clock     FD1P3AX     Q       debounce[4]     1.108       473.649
i_Trigger.debounce[5]      top|osc_clk_inferred_clock     FD1P3AX     Q       debounce[5]     1.108       473.649
=================================================================================================================


Ending Points with Worst Slack
******************************

                                   Starting                                                         Required            
Instance                           Reference                      Type        Pin     Net           Time         Slack  
                                   Clock                                                                                
------------------------------------------------------------------------------------------------------------------------
i_Trigger.cmd                      top|osc_clk_inferred_clock     FD1P3AX     SP      cmd_RNO_0     480.298      472.163
i_PISOsr.data_register_1_.II_0     top|osc_clk_inferred_clock     FD1S3DX     D       fb            480.664      472.506
i_PISOsr.data_register_1_.II_1     top|osc_clk_inferred_clock     FD1S3BX     D       fb            480.664      472.506
i_PISOsr.data_register_2_.II_0     top|osc_clk_inferred_clock     FD1S3DX     D       fb_0          480.664      472.506
i_PISOsr.data_register_2_.II_1     top|osc_clk_inferred_clock     FD1S3BX     D       fb_0          480.664      472.506
i_PISOsr.data_register_3_.II_0     top|osc_clk_inferred_clock     FD1S3DX     D       fb_1          480.664      472.506
i_PISOsr.data_register_3_.II_1     top|osc_clk_inferred_clock     FD1S3BX     D       fb_1          480.664      472.506
i_PISOsr.data_register_4_.II_0     top|osc_clk_inferred_clock     FD1S3DX     D       fb_2          480.664      472.506
i_PISOsr.data_register_4_.II_1     top|osc_clk_inferred_clock     FD1S3BX     D       fb_2          480.664      472.506
i_PISOsr.data_register_5_.II_0     top|osc_clk_inferred_clock     FD1S3DX     D       fb_3          480.664      472.506
========================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            0.472
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         480.298

    - Propagation time:                      8.134
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 472.163

    Number of logic level(s):                9
    Starting point:                          i_Prescaler.counter[0] / Q
    Ending point:                            i_Trigger.cmd / SP
    The start point is clocked by            top|osc_clk_inferred_clock [rising] on pin CK
    The end   point is clocked by            top|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
i_Prescaler.counter[0]                   FD1S3AX      Q        Out     1.108     1.108       -         
counter[0]                               Net          -        -       -         -           3         
i_Prescaler.un2_counter_cry_0_0          CCU2D        A1       In      0.000     1.108       -         
i_Prescaler.un2_counter_cry_0_0          CCU2D        COUT     Out     1.545     2.652       -         
un2_counter_cry_0                        Net          -        -       -         -           1         
i_Prescaler.un2_counter_cry_1_0          CCU2D        CIN      In      0.000     2.652       -         
i_Prescaler.un2_counter_cry_1_0          CCU2D        COUT     Out     0.143     2.795       -         
un2_counter_cry_2                        Net          -        -       -         -           1         
i_Prescaler.un2_counter_cry_3_0          CCU2D        CIN      In      0.000     2.795       -         
i_Prescaler.un2_counter_cry_3_0          CCU2D        COUT     Out     0.143     2.938       -         
un2_counter_cry_4                        Net          -        -       -         -           1         
i_Prescaler.un2_counter_cry_5_0          CCU2D        CIN      In      0.000     2.938       -         
i_Prescaler.un2_counter_cry_5_0          CCU2D        COUT     Out     0.143     3.081       -         
un2_counter_cry_6                        Net          -        -       -         -           1         
i_Prescaler.un2_counter_cry_7_0          CCU2D        CIN      In      0.000     3.081       -         
i_Prescaler.un2_counter_cry_7_0          CCU2D        S0       Out     1.621     4.702       -         
un2_counter_cry_7_0_S0                   Net          -        -       -         -           2         
i_Prescaler.Prescaler\.un9_counter_6     ORCALUT4     C        In      0.000     4.702       -         
i_Prescaler.Prescaler\.un9_counter_6     ORCALUT4     Z        Out     1.017     5.718       -         
un9_counter_6                            Net          -        -       -         -           1         
i_Prescaler.Prescaler\.un9_counter       ORCALUT4     D        In      0.000     5.718       -         
i_Prescaler.Prescaler\.un9_counter       ORCALUT4     Z        Out     1.350     7.069       -         
un9_counter                              Net          -        -       -         -           27        
i_Prescaler.clkout_RNIA428               ORCALUT4     B        In      0.000     7.069       -         
i_Prescaler.clkout_RNIA428               ORCALUT4     Z        Out     0.449     7.518       -         
clkout_RNIA428                           Net          -        -       -         -           16        
i_Trigger.cmd_RNO_0                      ORCALUT4     A        In      0.000     7.518       -         
i_Trigger.cmd_RNO_0                      ORCALUT4     Z        Out     0.617     8.134       -         
cmd_RNO_0                                Net          -        -       -         -           1         
i_Trigger.cmd                            FD1P3AX      SP       In      0.000     8.134       -         
=======================================================================================================




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                       Starting                                   Arrival            
Instance                               Reference     Type       Pin     Net       Time        Slack  
                                       Clock                                                         
-----------------------------------------------------------------------------------------------------
i_PISOsr.data_register_1_.res_lat      System        FD1S1D     Q       o3_14     0.972       476.083
i_PISOsr.data_register_12_.res_lat     System        FD1S1D     Q       o3        0.972       476.083
i_PISOsr.data_register_14_.res_lat     System        FD1S1D     Q       o3_1      0.972       476.083
i_PISOsr.data_register_15_.res_lat     System        FD1S1D     Q       o3_2      0.972       476.083
i_PISOsr.data_register_16_.res_lat     System        FD1S1D     Q       o3_3      0.972       476.083
i_PISOsr.data_register_2_.res_lat      System        FD1S1D     Q       o3_9      0.972       477.100
i_PISOsr.data_register_3_.res_lat      System        FD1S1D     Q       o3_10     0.972       477.100
i_PISOsr.data_register_4_.res_lat      System        FD1S1D     Q       o3_11     0.972       477.100
i_PISOsr.data_register_5_.res_lat      System        FD1S1D     Q       o3_12     0.972       477.100
i_PISOsr.data_register_6_.res_lat      System        FD1S1D     Q       o3_13     0.972       477.100
=====================================================================================================


Ending Points with Worst Slack
******************************

                                    Starting                                                     Required            
Instance                            Reference     Type        Pin     Net                        Time         Slack  
                                    Clock                                                                            
---------------------------------------------------------------------------------------------------------------------
i_PISOsr.empty                      System        FD1P3AX     D       un16_data_register_0_0     480.858      476.083
i_PISOsr.data_register_13_.II_0     System        FD1S3DX     D       fb_11                      480.664      477.442
i_PISOsr.data_register_13_.II_1     System        FD1S3BX     D       fb_11                      480.664      477.442
i_PISOsr.data_register_14_.II_0     System        FD1S3DX     D       fb_12                      480.664      477.442
i_PISOsr.data_register_14_.II_1     System        FD1S3BX     D       fb_12                      480.664      477.442
i_PISOsr.data_register_1_.II_0      System        FD1S3DX     D       fb                         480.664      477.450
i_PISOsr.data_register_1_.II_1      System        FD1S3BX     D       fb                         480.664      477.450
i_PISOsr.data_register_2_.II_0      System        FD1S3DX     D       fb_0                       480.664      477.450
i_PISOsr.data_register_2_.II_1      System        FD1S3BX     D       fb_0                       480.664      477.450
i_PISOsr.data_register_3_.II_0      System        FD1S3DX     D       fb_1                       480.664      477.450
=====================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
      Requested Period:                      480.769
    - Setup time:                            -0.089
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         480.858

    - Propagation time:                      4.775
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 476.083

    Number of logic level(s):                4
    Starting point:                          i_PISOsr.data_register_1_.res_lat / Q
    Ending point:                            i_PISOsr.empty / D
    The start point is clocked by            System [rising] on pin CK
    The end   point is clocked by            top|osc_clk_inferred_clock [rising] on pin CK

Instance / Net                                              Pin      Pin               Arrival     No. of    
Name                                           Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------
i_PISOsr.data_register_1_.res_lat              FD1S1D       Q        Out     0.972     0.972       -         
o3_14                                          Net          -        -       -         -           1         
i_PISOsr.data_register_1_.res_lat_RNI0LO11     ORCALUT4     C        In      0.000     0.972       -         
i_PISOsr.data_register_1_.res_lat_RNI0LO11     ORCALUT4     Z        Out     1.153     2.125       -         
data_register[1]                               Net          -        -       -         -           3         
i_PISOsr.PISOsr\.un16_data_register_12         ORCALUT4     B        In      0.000     2.125       -         
i_PISOsr.PISOsr\.un16_data_register_12         ORCALUT4     Z        Out     1.017     3.141       -         
un16_data_register_12                          Net          -        -       -         -           1         
i_PISOsr.PISOsr\.un16_data_register_21         ORCALUT4     A        In      0.000     3.141       -         
i_PISOsr.PISOsr\.un16_data_register_21         ORCALUT4     Z        Out     1.017     4.158       -         
un16_data_register_21                          Net          -        -       -         -           1         
i_PISOsr.PISOsr\.un16_data_register            ORCALUT4     D        In      0.000     4.158       -         
i_PISOsr.PISOsr\.un16_data_register            ORCALUT4     Z        Out     0.617     4.775       -         
un16_data_register_0_0                         Net          -        -       -         -           1         
i_PISOsr.empty                                 FD1P3AX      D        In      0.000     4.775       -         
=============================================================================================================



##### END OF TIMING REPORT #####]

Constraints that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)


Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 144MB)

---------------------------------------
Resource Usage Report
Part: lcmxo2_1200ze-1

Register bits: 88 of 1280 (7%)
Latch bits:      16
PIC Latch:       0
I/O cells:       14
Block Rams : 2 of 7 (28%)


Details:
AND2:           1
CCU2D:          10
DP8KC:          2
FADD2B:         4
FD1P3AX:        9
FD1P3BX:        2
FD1P3DX:        32
FD1S1D:         16
FD1S3AX:        5
FD1S3BX:        17
FD1S3DX:        16
FD1S3IX:        6
FSUB2B:         9
GSR:            1
IB:             2
INV:            10
MUX21:          44
OB:             12
OFS1P3DX:       1
ORCALUT4:       94
OSCH:           1
PUR:            1
ROM16X1A:       2
VHI:            5
VLO:            5
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 144MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Apr 18 12:25:40 2018

###########################################################]