PAR: Place And Route Diamond (64-bit) 3.7.0.96.1.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Thu Apr 19 09:14:33 2018

C:/lscc/diamond/3.7_x64/ispfpga\bin\nt64\par -f BreakoutBoard_impl1.p2t
BreakoutBoard_impl1_map.ncd BreakoutBoard_impl1.dir BreakoutBoard_impl1.prf
-gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml


Preference file: BreakoutBoard_impl1.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            461.660      0            0.688        0            03           Complete


* : Design saved.

Total (real) run time for 1-seed: 3 secs 

par done!

Lattice Place and Route Report for Design "BreakoutBoard_impl1_map.ncd"
Thu Apr 19 09:14:33 2018


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.7.0.96.1.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF BreakoutBoard_impl1_map.ncd BreakoutBoard_impl1.dir/5_1.ncd BreakoutBoard_impl1.prf
Preference file: BreakoutBoard_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file BreakoutBoard_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga.
Package Status:                     Final          Version 1.41.
Performance Hardware Data Status:   Final          Version 33.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   15+4(JTAG)/108     18% used
                  15+4(JTAG)/108     18% bonded

   SLICE             30/640           4% used

   GSR                1/1           100% used
   OSC                1/1           100% used


Number of Signals: 115
Number of Connections: 268

Pin Constraint Summary:
   15 out of 15 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    TP2_c (driver: OSC_inst, clk load #: 27)


The following 1 signal is selected to use the secondary clock routing resources:
    TP2_c_enable_36 (driver: SLICE_13, clk load #: 0, sr load #: 0, ce load #: 13)

Signal D1_c is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
...................
Placer score = 9804.
Finished Placer Phase 1.  REAL time: 2 secs 

Starting Placer Phase 2.
.
Placer score =  9670
Finished Placer Phase 2.  REAL time: 2 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  PLL        : 0 out of 1 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "TP2_c" from OSC on comp "OSC_inst" on site "OSC", clk load = 27
  SECONDARY "TP2_c_enable_36" from F1 on comp "SLICE_13" on site "R7C14D", clk load = 0, ce load = 13, sr load = 0

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 1 out of 8 (12%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   15 + 4(JTAG) out of 108 (17.6%) PIO sites used.
   15 + 4(JTAG) out of 108 (17.6%) bonded PIO sites used.
   Number of PIO comps: 15; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 5 / 28 ( 17%)  | 3.3V       | -         |
| 1        | 10 / 26 ( 38%) | 2.5V       | -         |
| 2        | 0 / 28 (  0%)  | -          | -         |
| 3        | 0 / 26 (  0%)  | -          | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 2 secs 

Dumping design to file BreakoutBoard_impl1.dir/5_1.ncd.

0 connections routed; 268 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=TP1_c loads=9 clock_loads=3

Completed router resource preassignment. Real time: 3 secs 

Start NBR router at 09:14:36 04/19/18

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 09:14:36 04/19/18

Start NBR section for initial routing at 09:14:36 04/19/18
Level 4, iteration 1
8(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 461.660ns/0.000ns; real time: 3 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 09:14:36 04/19/18
Level 4, iteration 1
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 461.660ns/0.000ns; real time: 3 secs 
Level 4, iteration 2
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 461.660ns/0.000ns; real time: 3 secs 
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 461.660ns/0.000ns; real time: 3 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 09:14:36 04/19/18

Start NBR section for re-routing at 09:14:36 04/19/18
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 461.660ns/0.000ns; real time: 3 secs 

Start NBR section for post-routing at 09:14:36 04/19/18

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : 461.660ns
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=TP1_c loads=9 clock_loads=3

Total CPU time 2 secs 
Total REAL time: 3 secs 
Completely routed.
End of route.  268 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file BreakoutBoard_impl1.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 461.660
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.688
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 2 secs 
Total REAL time to completion: 3 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.