Map TRACE Report
Loading design for application trce from file breakoutboard_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200ZE
Package: TQFP144
Performance: 1
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga.
Package Status: Final Version 1.41.
Performance Hardware Data Status: Final Version 33.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.7.0.96.1
Thu Apr 19 09:14:33 2018
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o BreakoutBoard_impl1.tw1 -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml BreakoutBoard_impl1_map.ncd BreakoutBoard_impl1.prf
Design file: breakoutboard_impl1_map.ncd
Preference file: breakoutboard_impl1.prf
Device,speed: LCMXO2-1200ZE,1
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "TP2_c" 2.080000 MHz (0 errors) 1039 items scored, 0 timing errors detected.
Report: 64.487MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "TP2_c" 2.080000 MHz ;
1039 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 465.262ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i_Trigger/Trigger.debounce_i0_i3 (from TP2_c +)
Destination: FF Data in i_Trigger/Trigger.debounce_i0_i6 (to TP2_c +)
Delay: 15.075ns (49.4% logic, 50.6% route), 8 logic levels.
Constraint Details:
15.075ns physical path delay i_Trigger/SLICE_0 to i_Trigger/SLICE_3 meets
480.769ns delay constraint less
0.432ns DIN_SET requirement (totaling 480.337ns) by 465.262ns
Physical Path Details:
Data path i_Trigger/SLICE_0 to i_Trigger/SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.955 *r/SLICE_0.CLK to *er/SLICE_0.Q0 i_Trigger/SLICE_0 (from TP2_c)
ROUTE 2 e 1.905 *er/SLICE_0.Q0 to SLICE_37.B1 i_Trigger/Trigger.debounce_3
CTOF_DEL --- 0.923 SLICE_37.B1 to SLICE_37.F1 SLICE_37
ROUTE 3 e 1.905 SLICE_37.F1 to SLICE_32.A1 i_Trigger/n545
CTOF_DEL --- 0.923 SLICE_32.A1 to SLICE_32.F1 SLICE_32
ROUTE 3 e 1.905 SLICE_32.F1 to *r/SLICE_10.B1 i_Trigger/n604
CTOF_DEL --- 0.923 *r/SLICE_10.B1 to *r/SLICE_10.F1 i_Trigger/SLICE_10
ROUTE 1 e 1.905 *r/SLICE_10.F1 to *er/SLICE_2.B1 i_Trigger/n534
C1TOFCO_DE --- 1.795 *er/SLICE_2.B1 to *r/SLICE_2.FCO i_Trigger/SLICE_2
ROUTE 1 e 0.001 *r/SLICE_2.FCO to *r/SLICE_1.FCI i_Trigger/n474
FCITOFCO_D --- 0.317 *r/SLICE_1.FCI to *r/SLICE_1.FCO i_Trigger/SLICE_1
ROUTE 1 e 0.001 *r/SLICE_1.FCO to *r/SLICE_0.FCI i_Trigger/n475
FCITOFCO_D --- 0.317 *r/SLICE_0.FCI to *r/SLICE_0.FCO i_Trigger/SLICE_0
ROUTE 1 e 0.001 *r/SLICE_0.FCO to *r/SLICE_3.FCI i_Trigger/n476
FCITOF1_DE --- 1.298 *r/SLICE_3.FCI to *er/SLICE_3.F1 i_Trigger/SLICE_3
ROUTE 1 e 0.001 *er/SLICE_3.F1 to *r/SLICE_3.DI1 i_Trigger/Trigger.debounce_6_N_161_6 (to TP2_c)
--------
15.075 (49.4% logic, 50.6% route), 8 logic levels.
Report: 64.487MHz is the maximum frequency for this preference.
Report Summary
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----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "TP2_c" 2.080000 MHz ; | 2.080 MHz| 64.487 MHz| 8
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: TP1_c Source: i_Prescaler/SLICE_14.Q0 Loads: 9
No transfer within this clock domain is found
Clock Domain: TP2_c Source: OSC_inst.OSC Loads: 28
Covered under: FREQUENCY NET "TP2_c" 2.080000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1039 paths, 1 nets, and 259 connections (96.64% coverage)
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Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.7.0.96.1
Thu Apr 19 09:14:33 2018
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o BreakoutBoard_impl1.tw1 -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml BreakoutBoard_impl1_map.ncd BreakoutBoard_impl1.prf
Design file: breakoutboard_impl1_map.ncd
Preference file: breakoutboard_impl1.prf
Device,speed: LCMXO2-1200ZE,M
Report level: verbose report, limited to 1 item per preference
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Preference Summary
FREQUENCY NET "TP2_c" 2.080000 MHz (0 errors) 1039 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "TP2_c" 2.080000 MHz ;
1039 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.324ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q i_PISOsr/PISOsr.data_register_i0_i20 (from TP2_c +)
Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i21 (to TP2_c +)
Delay: 0.257ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.257ns physical path delay SLICE_25 to SLICE_25 meets
-0.067ns M_HLD and
0.000ns delay constraint requirement (totaling -0.067ns) by 0.324ns
Physical Path Details:
Data path SLICE_25 to SLICE_25:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.257 SLICE_25.CLK to SLICE_25.Q0 SLICE_25 (from TP2_c)
ROUTE 2 e 0.000 SLICE_25.Q0 to SLICE_25.M1 i_PISOsr/PISOsr.data_register_20 (to TP2_c)
--------
0.257 (100.0% logic, 0.0% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "TP2_c" 2.080000 MHz ; | 0.000 ns| 0.324 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: TP1_c Source: i_Prescaler/SLICE_14.Q0 Loads: 9
No transfer within this clock domain is found
Clock Domain: TP2_c Source: OSC_inst.OSC Loads: 28
Covered under: FREQUENCY NET "TP2_c" 2.080000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1039 paths, 1 nets, and 259 connections (96.64% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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