Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.7.0.96.1 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Thu Apr 19 09:44:30 2018 Command Line: synthesis -f BuggyVHDL_impl1_lattice.synproj -gui -msgset C:/Users/Detzler/Desktop/VHDL/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 1. The -t option is TQFP144. The -d option is LCMXO2-1200ZE. Using package TQFP144. Using performance grade 1. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200ZE ### Package : TQFP144 ### Speed : 1 ########################################################## Optimization goal = Balanced Top-level module name = top. Target frequency = 1.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data (searchpath added) -p C:/Users/Detzler/Desktop/VHDL/impl1 (searchpath added) -p C:/Users/Detzler/Desktop/VHDL (searchpath added) VHDL library = work VHDL design file = C:/Users/Detzler/Desktop/VHDL/Top.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/SiCoSiTable.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/PISOshiftReg.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/Prescaler.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/Trigger.vhd VHDL design file = C:/Users/Detzler/Desktop/VHDL/PrescalerSCK.vhd NGD file = BuggyVHDL_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now "C:/Users/Detzler/Desktop/VHDL/impl1". VHDL-1504 Analyzing VHDL file c:/users/detzler/desktop/vhdl/top.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/top.vhd(22): analyzing entity top. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/top.vhd(44): analyzing architecture top_arch. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/sicositable.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/sicositable.vhd(14): analyzing entity sicositable. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/sicositable.vhd(24): analyzing architecture structure. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/sicositable.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/sicositable.vhd(14): analyzing entity sicositable. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/sicositable.vhd(24): analyzing architecture structure. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/pisoshiftreg.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/pisoshiftreg.vhd(7): analyzing entity pisosr. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/pisoshiftreg.vhd(20): analyzing architecture pisosr_arch. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/prescaler.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/prescaler.vhd(7): analyzing entity prescaler. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/prescaler.vhd(17): analyzing architecture prescaler_arch. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/trigger.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/trigger.vhd(7): analyzing entity trigger. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/trigger.vhd(18): analyzing architecture trigger_arch. VHDL-1010 Analyzing VHDL file c:/users/detzler/desktop/vhdl/prescalersck.vhd. VHDL-1481 INFO - synthesis: c:/users/detzler/desktop/vhdl/prescalersck.vhd(7): analyzing entity prescalersck. VHDL-1012 INFO - synthesis: c:/users/detzler/desktop/vhdl/prescalersck.vhd(17): analyzing architecture prescalersck_arch. VHDL-1010 unit top is not yet analyzed. VHDL-1485 c:/users/detzler/desktop/vhdl/top.vhd(22): executing top(top_arch) WARNING - synthesis: c:/users/detzler/desktop/vhdl/top.vhd(49): net DACData[15] does not have a driver. VDB-1002 WARNING - synthesis: c:/users/detzler/desktop/vhdl/top.vhd(42): replacing existing netlist top(top_arch). VHDL-1205 Top module name (VHDL): top Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga. Package Status: Final Version 1.41. Top-level module name = top. WARNING - synthesis: c:/users/detzler/desktop/vhdl/top.vhd(138): Removing unused instance i_SiCoSiTable. VDB-5034 ######## Missing driver on net DACData[15]. Patching with GND. ######## Missing driver on net DACData[14]. Patching with GND. ######## Missing driver on net DACData[13]. Patching with GND. ######## Missing driver on net DACData[12]. Patching with GND. ######## Missing driver on net DACData[11]. Patching with GND. ######## Missing driver on net DACData[10]. Patching with GND. ######## Missing driver on net DACData[9]. Patching with GND. ######## Missing driver on net DACData[8]. Patching with GND. ######## Missing driver on net DACData[7]. Patching with GND. ######## Missing driver on net DACData[6]. Patching with GND. ######## Missing driver on net DACData[5]. Patching with GND. ######## Missing driver on net DACData[4]. Patching with GND. ######## Missing driver on net DACData[3]. Patching with GND. ######## Missing driver on net DACData[2]. Patching with GND. ######## Missing driver on net DACData[1]. Patching with GND. ######## Missing driver on net DACData[0]. Patching with GND. GSR instance connected to net n181. Applying 1.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in top_drc.log. Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file BuggyVHDL_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 51 of 1604 (3 % ) CCU2D => 10 FD1P3AX => 31 FD1P3AY => 3 FD1P3IX => 4 FD1S3AX => 3 FD1S3IX => 10 GSR => 1 IB => 2 LUT4 => 37 OB => 13 OSCH => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : TP2_c, loads : 48 Net : i_Prescaler/TP1_c, loads : 3 Clock Enable Nets Number of Clock Enables: 3 Top 3 highest fanout Clock Enables: Net : TP2_c_enable_12, loads : 2 Net : TP2_c_enable_36, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : TP2_c_enable_36, loads : 25 Net : i_Prescaler/n290, loads : 13 Net : TP2_c_enable_12, loads : 11 Net : i_Trigger/Trigger.debounce_2, loads : 6 Net : i_Trigger/Trigger.debounce_1, loads : 6 Net : i_Trigger/n244, loads : 6 Net : i_Trigger/Trigger.debounce_0, loads : 6 Net : i_PrescalerSCK/PrescalerSCK.counter_0, loads : 5 Net : TasterA_c, loads : 4 Net : i_Trigger/Trigger.debounce_6, loads : 4 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets TP1_c] | 1.000 MHz| 115.500 MHz| 2 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets TP2_c] | 1.000 MHz| 47.092 MHz| 7 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 71.082 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.468 secs --------------------------------------------------------------