Place & Route TRACE Report

Loading design for application trce from file breakoutboard_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200ZE
Package:     TQFP144
Performance: 1
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga.
Package Status:                     Final          Version 1.41.
Performance Hardware Data Status:   Final          Version 33.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.7.0.96.1
Thu Apr 19 09:14:36 2018

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 1 -sphld m -o BreakoutBoard_impl1.twr -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml BreakoutBoard_impl1.ncd BreakoutBoard_impl1.prf 
Design file:     breakoutboard_impl1.ncd
Preference file: breakoutboard_impl1.prf
Device,speed:    LCMXO2-1200ZE,1
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "TP2_c" 2.080000 MHz (0 errors)
  • 1039 items scored, 0 timing errors detected. Report: 52.331MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "TP2_c" 2.080000 MHz ; 1039 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i21 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i20 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_25 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_25: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R4C17D.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R4C17D.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i0 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i24 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_27 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_27: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R4C17C.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_27: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R4C17C.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i9 (to TP2_c +) Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_30 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_30: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C15D.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C15D.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i2 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i19 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_31 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_31: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C18D.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C18D.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i4 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i3 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_33 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C18B.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C18B.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i18 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i17 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_34 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_34: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C16B.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C16B.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i6 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i5 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_37 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_37: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C18A.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_37: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C18A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i14 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i13 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to i_PISOsr/SLICE_35 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to i_PISOsr/SLICE_35: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C17C.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to i_PISOsr/SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17C.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i23 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i22 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to i_PISOsr/SLICE_26 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C17A.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 461.660ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i22 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i16 (to TP2_c +) FF i_PISOsr/PISOsr.data_register_i0_i15 Delay: 18.539ns (25.1% logic, 74.9% route), 5 logic levels. Constraint Details: 18.539ns physical path delay i_PISOsr/SLICE_26 to SLICE_38 meets 480.769ns delay constraint less 0.000ns skew and 0.570ns CE_SET requirement (totaling 480.199ns) by 461.660ns Physical Path Details: Data path i_PISOsr/SLICE_26 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.955 R5C17A.CLK to R5C17A.Q0 i_PISOsr/SLICE_26 (from TP2_c) ROUTE 2 2.275 R5C17A.Q0 to R5C17D.A1 i_PISOsr/PISOsr.data_register_22 CTOF_DEL --- 0.923 R5C17D.A1 to R5C17D.F1 i_PISOsr/SLICE_36 ROUTE 1 2.295 R5C17D.F1 to R5C17D.B0 i_PISOsr/n30 CTOF_DEL --- 0.923 R5C17D.B0 to R5C17D.F0 i_PISOsr/SLICE_36 ROUTE 1 2.855 R5C17D.F0 to R7C14D.C0 i_PISOsr/n44 CTOF_DEL --- 0.923 R7C14D.C0 to R7C14D.F0 SLICE_13 ROUTE 3 1.083 R7C14D.F0 to R7C14D.C1 n600 CTOF_DEL --- 0.923 R7C14D.C1 to R7C14D.F1 SLICE_13 ROUTE 13 5.384 R7C14D.F1 to R5C15C.CE TP2_c_enable_36 (to TP2_c) -------- 18.539 (25.1% logic, 74.9% route), 5 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_26: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C17A.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 28 7.917 OSC.OSC to R5C15C.CLK TP2_c -------- 7.917 (0.0% logic, 100.0% route), 0 logic levels. Report: 52.331MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "TP2_c" 2.080000 MHz ; | 2.080 MHz| 52.331 MHz| 5 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: TP1_c Source: i_Prescaler/SLICE_14.Q0 Loads: 9 No transfer within this clock domain is found Clock Domain: TP2_c Source: OSC_inst.OSC Loads: 28 Covered under: FREQUENCY NET "TP2_c" 2.080000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1039 paths, 1 nets, and 259 connections (96.64% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.7.0.96.1 Thu Apr 19 09:14:36 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 1 -sphld m -o BreakoutBoard_impl1.twr -gui -msgset C:/Users/Detzler/Documents/BusPirate/promote.xml BreakoutBoard_impl1.ncd BreakoutBoard_impl1.prf Design file: breakoutboard_impl1.ncd Preference file: breakoutboard_impl1.prf Device,speed: LCMXO2-1200ZE,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "TP2_c" 2.080000 MHz (0 errors)
  • 1039 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "TP2_c" 2.080000 MHz ; 1039 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i20 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i21 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_25 to SLICE_25 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_25 to SLICE_25: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R4C17D.CLK to R4C17D.Q0 SLICE_25 (from TP2_c) ROUTE 2 0.364 R4C17D.Q0 to R4C17D.M1 i_PISOsr/PISOsr.data_register_20 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R4C17D.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_25: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R4C17D.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i2 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i3 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_31 to SLICE_33 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_31 to SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18D.CLK to R5C18D.Q1 SLICE_31 (from TP2_c) ROUTE 2 0.364 R5C18D.Q1 to R5C18B.M0 i_PISOsr/PISOsr.data_register_2 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18D.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i7 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i8 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_32 to SLICE_32 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_32 to SLICE_32: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18C.CLK to R5C18C.Q0 SLICE_32 (from TP2_c) ROUTE 2 0.364 R5C18C.Q0 to R5C18C.M1 i_PISOsr/PISOsr.data_register_7 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i3 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i4 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_33 to SLICE_33 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_33 to SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18B.CLK to R5C18B.Q0 SLICE_33 (from TP2_c) ROUTE 2 0.364 R5C18B.Q0 to R5C18B.M1 i_PISOsr/PISOsr.data_register_3 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i4 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i5 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_33 to SLICE_37 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_33 to SLICE_37: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18B.CLK to R5C18B.Q1 SLICE_33 (from TP2_c) ROUTE 2 0.364 R5C18B.Q1 to R5C18A.M0 i_PISOsr/PISOsr.data_register_4 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_37: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18A.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i17 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i18 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_34 to SLICE_34 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_34 to SLICE_34: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C16B.CLK to R5C16B.Q0 SLICE_34 (from TP2_c) ROUTE 2 0.364 R5C16B.Q0 to R5C16B.M1 i_PISOsr/PISOsr.data_register_17 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C16B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_34: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C16B.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i6 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i7 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_37 to SLICE_32 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_37 to SLICE_32: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18A.CLK to R5C18A.Q1 SLICE_37 (from TP2_c) ROUTE 2 0.364 R5C18A.Q1 to R5C18C.M0 i_PISOsr/PISOsr.data_register_6 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_37: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18A.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i5 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i6 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_37 to SLICE_37 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_37 to SLICE_37: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C18A.CLK to R5C18A.Q0 SLICE_37 (from TP2_c) ROUTE 2 0.364 R5C18A.Q0 to R5C18A.M1 i_PISOsr/PISOsr.data_register_5 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_37: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18A.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_37: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C18A.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.688ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i15 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i16 (to TP2_c +) Delay: 0.621ns (41.4% logic, 58.6% route), 1 logic levels. Constraint Details: 0.621ns physical path delay SLICE_38 to SLICE_38 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.688ns Physical Path Details: Data path SLICE_38 to SLICE_38: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C15C.CLK to R5C15C.Q0 SLICE_38 (from TP2_c) ROUTE 2 0.364 R5C15C.Q0 to R5C15C.M1 i_PISOsr/PISOsr.data_register_15 (to TP2_c) -------- 0.621 (41.4% logic, 58.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C15C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to SLICE_38: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C15C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.691ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q i_PISOsr/PISOsr.data_register_i0_i12 (from TP2_c +) Destination: FF Data in i_PISOsr/PISOsr.data_register_i0_i13 (to TP2_c +) Delay: 0.624ns (41.2% logic, 58.8% route), 1 logic levels. Constraint Details: 0.624ns physical path delay i_PISOsr/SLICE_36 to i_PISOsr/SLICE_35 meets -0.067ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.067ns) by 0.691ns Physical Path Details: Data path i_PISOsr/SLICE_36 to i_PISOsr/SLICE_35: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.257 R5C17D.CLK to R5C17D.Q1 i_PISOsr/SLICE_36 (from TP2_c) ROUTE 2 0.367 R5C17D.Q1 to R5C17C.M0 i_PISOsr/PISOsr.data_register_12 (to TP2_c) -------- 0.624 (41.2% logic, 58.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSC_inst to i_PISOsr/SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C17D.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSC_inst to i_PISOsr/SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 28 2.486 OSC.OSC to R5C17C.CLK TP2_c -------- 2.486 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "TP2_c" 2.080000 MHz ; | 0.000 ns| 0.688 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: TP1_c Source: i_Prescaler/SLICE_14.Q0 Loads: 9 No transfer within this clock domain is found Clock Domain: TP2_c Source: OSC_inst.OSC Loads: 28 Covered under: FREQUENCY NET "TP2_c" 2.080000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1039 paths, 1 nets, and 259 connections (96.64% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------