Author Topic: Lattice Radiant for iCE40UP FPGA series  (Read 6917 times)

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Offline imo

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Lattice Radiant for iCE40UP FPGA series
« on: March 07, 2018, 10:16:22 am »
As the new "Lattice Radiant" development system tailored for the iCE40UP3k/5k series has been mentioned briefly in other topics let us start a separate thread..

I've spent a few days comparing a verilog design (j1a cpu) under IceCube2 and Radiant. They changed the names and parameter's formats with all primitives in Radiant, thus you have to migrate an existing design from the IceCube2 (or IceStorm) to the Radiant first. It requires a lot of reading, however  ::)

As an example I've compared the building of an "identical verilog design" under IceCube2 and Radiant - a j1a (forth) cpu utilizing all bram and spram and 27 pins, running at 24MHz w/ internal oscillator (iCE40UP5k UPduino board):

Code: [Select]
Tool       Size(LUTs)  Time to build    maxClk est. [MHz]
==========================================================
IceCube2     2703         2:56           35  (34-36)
Radiant      2741         3:30           19  (15-20)
Note: time to build is +/-10secs, SynPro w/ default IceCube2 and Radiant setup, ring-osc commented out.

The Radiant provides rather conservative timing's estimates (similar to the IceStorm's ones), while IceCube2 is always pretty optimistic.
On silicon the Radiant binaries with 15-17MHz max clock estimates are not working properly, thus it seems the Radiant provides
much more realistic estimates.

Some first glance findings:

1. The Radiant offers a new INV primitive, therefore I've tried to create a ring oscillator made of 3 INVs (a part of a random generator). It does not synthesize with SynPro, it does with LSE (and it works on silicon).
Edit: Tech Support proposed a workaround, it works.

2. The Reveal Analyzer inserts an JTAG module into your design (together with an LA) - here the synthesis stops with an error indicating an unknown primitive "INV_c" wired in jtck signal.

3. The Reveal Analyzer knows the FT232H :)
Code: [Select]
INFO - cable[0]=FTUSB-0,USB2,Single RS232-HS Location 0000The logic analyzer has not been tested yet, see point 2.

« Last Edit: March 08, 2018, 07:56:15 am by imo »
 

Offline ehughes

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #1 on: March 07, 2018, 01:45:09 pm »
Quote
The Reveal Analyzer knows the FT232H

Forgive my ignorance as I am new to Lattice products,  are they using the FT232H as a JTAG interface?       
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #2 on: March 07, 2018, 01:47:45 pm »
Yes (hopefully, they offer a box, most probably with FTxxxx inside, the Programmer works with FT232H too). Afaik the Reveal Inserter configures your on-chip Logic Analyzer (you set the LA buffer depth, signals to watch, triggers) and creates a verilog/vhdl module with JTAG interface and LA for you.
You have to add the file into "Debug" folder, set the JTAG pins as you wish (?), and run the build. You have to create a sampling clock as well (via PLL for example, max 200MHz). Currently it uses EBR for the LA buffer, perhaps they will do with SPRAM as well (ie. the UP5k has got 15kB of EBR and 128kB of SPRAM).
Then you run the Reveal Analyzer.
It is something similar to the ChipScope (Xilinx).
« Last Edit: March 07, 2018, 02:05:50 pm by imo »
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #3 on: March 07, 2018, 10:34:34 pm »
With FT232H - the session (counter_reveal example, with different JTAG pins):
Code: [Select]
INFO - runProject on device [JTAG_SOFT] using C:/Lattice/counter_reveal/my1.rva [insert.rvl]
INFO - Connecting cableserver to run Reveal debugger....
INFO - Connecting core0....
INFO - Configuring core0....
INFO - pattern readout passed!
INFO - signature from core0 passed!
INFO - Configuring in burst mode....
INFO - finished configuration of core0
INFO - Starting all active cores....
RvaThread: running...
INFO - Running all active cores....
INFO - Polling trigger memory of core0....
INFO - Downloading trigger memory of core0....
INFO - Uploading in burst mode....
INFO - finished download trigger memory of core0
INFO - All messages logged in file C:/Lattice/counter_reveal/impl1/reveal_debug.log

Code: [Select]
Wiring FT232H <-> Reveal Analyzer

FT232H       FPGA pin*     softJTAG     FPGA pin dir
====================================================
AD0            26            TCK          input
AD1            27            TDI          input
AD2            31            TDO          output
AD3            32            TMS          input
*User may define, other pins not tested yet..

And the picture below.. :)
« Last Edit: March 07, 2018, 11:02:44 pm by imo »
 

Offline Cerebus

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #4 on: March 08, 2018, 01:46:00 am »
The Radiant provides rather conservative timing's estimates (similar to the IceStorm's ones), while IceCube2 is always pretty optimistic.
On silicon the Radiant binaries with 15-17MHz max clock are not working properly, thus it seems the Radiant provides
much more realistic estimates.

Confused. You say the conservative timings are more realistic, but then you say that a physical clock that meets those estimates does not work.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #5 on: March 08, 2018, 06:51:57 am »
As I wrote above 24MHz internal clock was used with the tests.. Those were 15-17MHz max clock "estimates".. Fixed above. Thanks.
« Last Edit: March 08, 2018, 07:02:50 am by imo »
 

Online MasterTech

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #6 on: March 22, 2018, 05:25:55 pm »
I can't download Icecube2, web is not working, anyone can get through the download link on this page?

http://www.latticesemi.com/iCEcube2

« Last Edit: March 22, 2018, 05:28:12 pm by MasterTech »
 

Offline Cerebus

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #7 on: March 22, 2018, 05:47:06 pm »
It's a problem at their end, give it a day and try again.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 
The following users thanked this post: MasterTech

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #8 on: March 22, 2018, 06:01:15 pm »
Works fine here.
Btw you have to click on the "IceCube2..." (see below) in order to start downloading.
"Download Selected as Zip File" does not work here..
« Last Edit: March 22, 2018, 06:03:59 pm by imo »
 

Online MasterTech

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #9 on: March 22, 2018, 06:17:59 pm »
Works fine here.

Not here, What OS/browser are u on?
I'm on Macos 10.13, Safari 11 and Firefox 59 and it doesn't load.
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #10 on: March 22, 2018, 06:35:53 pm »
Win7 64bit, Firefox 59.0.1
 

Offline Cerebus

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #11 on: March 22, 2018, 06:42:43 pm »
Gentlemen, it may depend on where you are, it's probably going through an edge caching content delivery network at some point. When I try to access over HTTPS (which is where you were having a problem, during login) I get an explicit reset sent by the far end. HTTP (without the S) goes through fine. That makes we think there's a far end problem that will probably go away of its own accord.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline helius

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #12 on: March 22, 2018, 06:42:56 pm »
They may have enabled TLS1.3 only
which, indeed, causes special problems for middleboxes
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #13 on: March 22, 2018, 06:47:22 pm »
The pages I mess with are http: and the file download is from http:
 

Online MasterTech

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #14 on: March 22, 2018, 08:45:08 pm »
Thanks people, Cerebus u were right, after a few hours problem solved itself
 

Offline Cerebus

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #15 on: March 22, 2018, 09:56:14 pm »
Thanks people, Cerebus u were right, after a few hours problem solved itself

[ Breathes on nails, buffs them on shirt. ]  :)
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline Scrts

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #16 on: September 04, 2018, 04:47:25 pm »
Hello,
I've started to work on these FPGAs a little bit (up5k) and going from Altera to Lattice seems to be going back. A lot.
First of all, I've installed Diamond, which was my mistake - the ice40 devices are not supported. Then I've installed IceCube2, which doesn't even have a color coded editor. They didn't even bother to put menu item to instantiate an on-chip oscillator. However, at least I could instantiate I2C/SPI core going through the menu.
Now once I had to do some on-chip debug, I've started to look into Reveal logic analyzer, which documentation says that it fits into up5k FPGA. Now the problem is that you cannot instantiate it in IceCube2 and need Lattice Radiant software.
Ok, downloaded that. The editor seems to be good, the menus are nice, the compile time is also quick and I see that I can run Reveal Inserter. But wait, where is the I2C/SPI or On-chip oscillator inserters? None. It doesn't even recognize the old instantiation in the code from IceCube2. So you need two independent software packages to run two features, but you cannot get compatibility between the project files and source codes? This sounds like 80s... :--
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #17 on: September 04, 2018, 04:59:41 pm »
Yes, the IceCube2/IceStorm and the Radiant are not compatible anymore. It has been discussed in a different thread, afaik.
 

Offline SiliconWizard

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #18 on: September 04, 2018, 05:11:26 pm »
They have changed a lot of stuff between the two - for the better IMO, but I realize it would be an annoyance for people having to use older projects.
Radiant's online help helps figuring out the new names/components. Taking a look at the hdl libraries can also help: you can find the source code with the components declaration in the following directory:
Code: [Select]
C:\lscc\radiant\1.0\cae_library\synthesis
But there is no "porting guideline" as of yet that I know of.
 

Offline Scrts

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #19 on: September 04, 2018, 05:39:42 pm »
So which one you use? It seems like IceCube2 + Notepad++ seems to be the best option for design so far.
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #20 on: September 04, 2018, 05:44:36 pm »
They issued SP1 for Radiant recently, so it seems they mess more with Radiant than with IceCube..
The changes are not huge, however - there is an example comparing IceCube/IceStorm/Radiant here..
« Last Edit: September 04, 2018, 05:47:58 pm by imo »
 

Offline Scrts

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #21 on: September 04, 2018, 05:45:32 pm »
They issued SP1 for Radiant recently, so it seems they mess more with Radiant than with IceCube..

5MB patch on 600MB software doesn't sound like an SP... Probably just a quick bandaid on something urgent.
 

Offline ilik

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #22 on: December 20, 2018, 08:31:13 am »
Anyone messed with Reveal Analyzer? it doesn't seem to work. gives errors "incorrect pattern readout" when trying to collect data. everything else works fine, fpga gets programmed and everything.
 

Offline imo

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #23 on: December 20, 2018, 05:57:19 pm »
See Reply N3 in this thread..
 

Offline ilik

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Re: Lattice Radiant for iCE40UP FPGA series
« Reply #24 on: December 20, 2018, 09:23:14 pm »
yes but on comment 3, you discuss ice40 ultra plus 5k breakout board where FTDI is already soldered. i have my own PCB and am trying to JTAG it by  HW-USBN-2B programmer. i did followed  HW-USBN-2 pinout manual, and connected soft jtag pins according to it. but when i try to analyze it by reveal analyzer it gives error: "incorrect pattern readout" . error log file shows readout:

#pattern readout = ffff
#pattern expected = A5A5

i have read in the reveal troubleshooting guide that all ffff mean there is a clocking problem:

"The third cause for the incorrect signature error message is when the sample
clock is not correctly connected to the debug logic. This can occur if a
problem happens in the implementation flow. The signature read from the
device will be all ones in this situation. To resolve this, the post-map netlist
needs to be viewed directly to determine the root cause."

reeeally? now i have to mess with netlist and figure out which clock should go where? for this i will have to study entire soft jtag protocol how else will i understand how to clock it properly. (my sample clock is basic onboard HSOSC 48mhz and yes, it is turned on, checked on testpoint).

PS. Lattice refuses to Tech support individuals that are not registered to their organisations list.
« Last Edit: December 20, 2018, 09:28:44 pm by ilik »
 


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