I've seen a number of projects using a vintage CPU and a microcontroller, in particular an AVR one. This certainly isn't the first or only project of this kind.
More recently, I've seen a project using a 6502 and a RP2040 as an EPROM emulator, using the PIO for interfacing it. Fun and neat.
Although vintage CPU boards required a significant number of logic parts, that's part of the vintage spirit. I for one am not sure I see the point of designing something "vintage" with a mix of old and modern chips. If you're not going to go 100% vintage, why not go all the way and just implement everything in a FPGA or as emulation on a recent MCU/CPU? Of course, to each their own...!
While not a vintage CPU, in that spirit, I have a back-burner project to implement the famous Delta Lab Effectron II digital audio delay in a 500-series plug-in rack module.
For those not familiar with this particular work of genius: it's a single channel delay with a maximum delay time of one second (actually 1024 ms). A bank of old EDO DRAM is used to implement the delay. A state machine/sequencer to drive the memory and implement the sampler is made from various 4000-series CMOS gates, counters and flip-flops. An RC oscillator and CD4528 VCO chip set the clock frequency which is varied by a pot. The clock runs from 250 kHz to 1 MHz.
The company was called Delta Lab because the sampler used delta modulation. It is basically a textbook implementation of how you'd implement a one-bit oversampling converter out of MSI parts (4016 switches, 4013 flip-flops, 4015 shift registers, 311 comparators, TL082 op-amps).
Here is the cool part: they don't bother to decimate the one-bit high-frequency conversion result down to multi-bit-wide but lower sample rate conversion result. Instead, they put that one bit result into the DRAM. At the output, they take the shifted one bit result and run it through an identical-to-the-sampler recovery circuit. The DRAM is basically one very long one-bit shift register. Coarse time delay is set by front-panel switches, with 16 ms, 64 ms, 256 ms and 1024 ms options. You get in-between delay times by changing the clock frequency! So you get fun things when you change the delay time when there is signal in the memory. There's also an infinite hold option, which simply takes the output of the shift register and feeds it right back into the input. An LFO wiggles the sample clock frequency for cool phasey effects.
My idea, then, is to retain the idiosyncratic part of the design that makes it what it is: the discrete (well, MSI logic) implementation of the modulator and the VCO clocking. The memory can be implemented in block RAM in a small FPGA, and the rest of the control stuff can be done in the FPGA, too.
So it's an emulator but retains the neat features, and fits into a form factor the studio people like.
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