I've got a little tda1543 (
http://www.qlshifi.com/jszl/TDA1543.pdf ) and realised that my in stock mcu's : attiny13/85 or atmega328 are unable to drive it. This little dac require 9.6 MHz data line, attiny should be able to do it if cpu freq = 9.6 * 2 = 19.2 MHz, but then it doesn't have time to do anything else, and data buffer gonna be limited to ram size, which is 512 bytes for attiny85. I can dedicate one attiny85 to drive the dac, and upload data to it through interrupt + i2c, but this sounds like extreme hobby masochism - bit banging 9.6 MHz on breadboard
Is there any more sane way for hobbyist to drive i2s but fpga ? I saw some references to this board
http://www.cypress.com/?rID=99916, it can drive each pin at 100 mhz and have fifo and arm core.
One of the smallest STM32, the STM32F031 (Cortex M0) can do this (it has an in-built I2S controller).
This should be a good excuse for you to start with Cortex MCUs. STM32 evaluation boards are incredibly cheap.
You need to use the USART (universal synchronous asynchronous receiver transmitter) module. This allows you to send a bye at a time without bit banging data or clock lines. You will need to set up the click correctly (rising/falling edge). You will also need to bit bang the LRCLK (WCLK) line, but that is only one transition each 32 bits. It can be done but the tricks are low jitter on the LRCLK and finding enough spare cycles to obtain the next sample data.
One of the smallest STM32, the STM32F031 (Cortex M0) can do this (it has an in-built I2S controller).
This should be a good excuse for you to start with Cortex MCUs. STM32 evaluation boards are incredibly cheap.
Bought
http://www.ebay.com/itm/151289777040, will receive it in couple of days
You need to use the USART (universal synchronous asynchronous receiver transmitter) module. This allows you to send a bye at a time without bit banging data or clock lines. You will need to set up the click correctly (rising/falling edge). You will also need to bit bang the LRCLK (WCLK) line, but that is only one transition each 32 bits. It can be done but the tricks are low jitter on the LRCLK and finding enough spare cycles to obtain the next sample data.
It's actually works, but pushing limits of atmega328p for sure, I only have it on arduino nano board (and while playing with it I've blown up a current limiting resistor
), and there is a 16 MHz crystal, but well, 8 MHz is sorta enough.
This is my current source code
https://gist.github.com/jimon/f6e50913e6a8b6bea28dI've found it's really tricky to implement I2S because LSB of word comes
after WS edge
, so my current implementation is "incorrect", it can't set least significant bit. Looks like there is no FIFO at all, just one output register. So it's kinda very limited because instead of bit banging, cpu does "register banging"
Sure software FIFO is possible, but with delays to prepare buffer.
PS. I haven't found a flag to change MSB\LSB order in raw USART. There are only flags in SPI mode.
I've got a little tda1543 ( http://www.qlshifi.com/jszl/TDA1543.pdf ) and realised that my in stock mcu's : attiny13/85 or atmega328 are unable to drive it. This little dac require 9.6 MHz data line, attiny should be able to do it if cpu freq = 9.6 * 2 = 19.2 MHz, ...
That's the maximum bitclock it can handle (9.2Mhz, not 9.6), which corresponds to a 24bit stereo I2S stream at 192kHz sampling rate (48 bits per stereo sample x 192000 samples per second = 9216000 bps), but you're not required to run it at that speed. If you run it at standard "CD-quality" 16-bit stereo, 44.1kHz, your bitclock would reduce to a slightly more manageable rate of about 1.4Mhz.
But yes, the STM32 parts are great for this. However, there's nothing magic about them. I2S is not that different from SPI, and you'll notice that the STM32 micro actually uses an SPI peripheral for I2S. (There might be a dedicated I2S PLL to get the clock rate as accurate as possible, but that's about it.)
If you want to use it for good audio quality (not only voice or other low quality, low bandwidth stuff), better get a different dac with buildin oversampling:
The TDA1543 is designed to be used with an digital oversampling filter, otherwise you need a brickwall antialiasing analogue filter after the dac which is almost impossible.
Using a more reasonable analogue lowpass filter, you need a samplerate of at least 4x the maximum output frequency.
Most modern dacs support not only I2S but also MSB or LSB aligned data that can easily driven using a standard spi interface.
