First question: your Arduino code is configured to react to a
rising edge on CS, and your CH32V code is also configuring EXTI for a rising edge interrupt. Are you sure that's what you need? Chip-select on SPI is conventionally active-low, with the slave device being selected by a low level on CS, therefore you typically want the slave to react to a
falling edge on CS. Do you have some unusual master device that uses active-high polarity on CS?
As pcprogrammer said, in your CH32V code you aren't explicitly configuring PC1, but all GPIO pins are configured as inputs by default, so that probably isn't an issue (but you should always explicitly configure all the GPIOs being used, even if in the same way as default). However, a bigger issue is that if you're using PC1 for CS, and configuring the SPI for hardware NSS, then this
only supports active-low CS signals. If you do indeed need active-high CS, then you can't use hardware NSS.
Your apparent requirement for active-high CS also conflicts with how you are configuring GPIO PD1 with
GPIO_Mode_IPU, which enables the internal pull-
up resistor. This only suitable for active-low CS - you would want
GPIO_Mode_IPD for active-high CS.
One other issue I can see in your code is your
EXTI7_0_IRQHandler code is flawed for hardware NSS usage. In it you are only setting
isrIndex to zero, but you also really need to put the first byte of data into the SPI data register
before the master starts outputting SCK. In hardware NSS mode, as soon as the slave SPI peripheral starts receiving clock, it automatically starts transmitting the contents of the data register. But you're only writing TX data to the SPI data register upon each newly-received byte coming in; your first transmitted byte on MISO will be whatever random value happens to be in the SPI data register. You should probably add a
SPI_I2S_SendData(SPI1, TxData[isrIndex]) call to
EXTI7_0_IRQHandler.
You could probably also do with modifying your SPI interrupt handling. As I said above, you're only writing TX bytes to the SPI data register upon RXNE IRQ, but that is only fired on the last bit of each byte being received. I'm not sure whether that leaves enough time to put new TX data in the SPI data register for the next to go out on MISO. You should probably instead also handle SPI TXE interrupts, and write the next TX byte to the SPI data register there. That way you can be sure the correct data is ready to be sent in plenty of time.
One last thing I'll mention is that you may not need to use an additional GPIO (i.e. PD1) to also have an external interrupt on the CS line. You can probably set up the EXTI on PC1. I don't think there's anything stopping you using PC1 for SPI NSS
and enabling an EXTI on it too.
Are you sure HPE is enabled?
FYI, HPE is enabled by default in the WCH standard start-up assembly code. It looks like OP has adapted one of the SPI example projects from the WCH EVT, so will almost certainly be using that.