MCU with only one VDD/VSS pin

[Saimoun]

Hi

Just having a look at the GD32L233 - new low-power MCU from GigaDevice. Really awesome IMO.

On the big package (64 pins), there is literally one VDD pin and one VSS pin. Doesn't that mean the overall current the MCU can handle is pretty low?

GigaDevice is not great at giving detailed datasheets, I remember on some ST datasheets seeing a "max current flowing through the device", i.e. combination of all pins should not exceed something like +/-150mA. This one having only one pin I would guess this limit is pretty low? The only info I have on this GD MCU datasheet is that each pin should not go above +/-25mA. But I doubt the MCU will like it if I draw 20mA out of every single GPIO.

Would love to hear your thoughts - datasheet is attached.

Thanks
Simon

[wraper]

You can take max power dissipation spec and go from there.

[sokoloff]

The current limits are overall power dissipation and current handling of the transistors inside, not the pins themself. (There are SMD voltage regulators rated at/over an amp per pin.)

[T3sl4co1l]

You can take max power dissipation spec and go from there.

Not... really...

Say there are 50 pins actively sinking current.  Say each pin driver is about 50 ohms Rds(on) (which is a bit on the high end for average CMOS, in sinking direction / for the NMOS, or a bit on the low for sourcing / PMOS).  All 50 effectively work in parallel, and dissipate in total the rated dissipation of the chip.  Which, let's say it's 1W just for a SWAG.  50 pins in parallel, 50 ohms each, is 1 ohm equivalent.  1W into 1 ohm is 1V and 1A.  Even if half of that is sourcing from VDD instead of sinking to VSS, that's a ridiculous amount of current.  Okay, say it's 0.1W instead; even quite small MCUs should handle that just fine.  Well, 1/10 power is 1/sqrt(10) voltage and current: about 320mA, or 160mA each if split half-and-half.  Which still sounds unreasonable given most device ratings.

It's probably a good idea to buffer anything where you need a lot of loads on that thing.

On the other hand, I'm guessing it's cheap enough you might not care if it only lasts a few years then dies due to say electromigration..?

The current limits are overall power dissipation and current handling of the transistors inside, not the pins themself. (There are SMD voltage regulators rated at/over an amp per pin.)

Right, but they're rated for it.

And other MCUs, logic, etc. are rated at 150, 50, even 20mA per pin.  Even less (DC) for a lot of FPGAs, for that matter.  Surely they would rate them for more if they're simply not getting hot and that's the end of it!

It's not about dissipation, or not just.  It depends on the number of bondwires.  How big/many pads they hit.  How big the interconnects off them.  How many metal layers.  Etc.  A lot more goes into it than just power dissipation!

Tim

[ataradov]

Even a single pin can handle a lot of current. The reason you see a lot of pins on other MCUs is decoupling. And how this is handled depends on the way device is designed. It can have capacitors in package (rare and expensive, but possible) or some consideration on the die itself. Or they characterized the device and assumed a bit more risk than typical.

[Saimoun]

That's a lot of useful replies guys, thanks so much.

Tim going deep into details that's so great - learning a lot here.

I just checked the total current I would use which would be (absolute worst case):
* sourcing 18mA (3 sourcing LEDs)
* sinking 12mA (2 sinking LEDs)

Then you gotta add a few digital signals at 0.1mA ish, and the CPU+peripherals usage which is <10mA.

So nothing crazy there, and I am way below the values I saw on other similar MCUs. I just got worries because of the single VDD/VSS pin, but as I understood from your answers the max current the MCU can handle is unrelated to that.

[wraper]

Also if there is only one VDD terminal, it does not mean there is only a single bond wire for power. There can be multiple bond wires from a single terminal connected to different parts of the chip, or several bond wires in parallel.

[SiliconWizard]

Well, yeah, they may have been tight on pin budget for this 64-pin package and decided to dedicate only one pin to VCC and GND, while they may reserve the possibility to release versions in different packages with more pins on which they would distribute power across more pins.

That said, the datasheet should mention how much max current those pins are able to handle. But as a more general thought, I think it's a bit off to consider a flagged "low-power" MCU for applications that would require delivering a relatively high current from GPIOs. Just doesn't add up much.

[Saimoun]

But as a more general thought, I think it's a bit off to consider a flagged "low-power" MCU for applications that would require delivering a relatively high current from GPIOs. Just doesn't add up much.

So are you saying the MCU is a bad choice for +/-15mA of current usage?

[T3sl4co1l]

Without additional information, I would assume the same current rating as every other pin.  So, probably 10 or 20mA is about as high as it should go.  15 is in that range, so, probably OK.

The other thing that's a pain, is EMI.  This is true regardless of how many bondwires they've used: bypassing can't be any better than the two pins, a single bypass cap (or however many you try and stack together), the pin lengths, and the return path.  Every CPU cycle, every pin toggle, can be "heard" through every other output pin.  Definitely a case to avoid routing GPIOs (particularly outputs) to the outside world.  They'll probably be dirty in the 10s of mV range.  At the very least, filter such signals before going out to an unshielded cable (and, needless to say, whatever ESD protection that might also want to have).

That's not usually a problem (use proper interfaces where possible e.g. RS-232, 422/485, etc.), but it can be a concern in that intermediate space where you have long traces running across a wide board, or short interconnects going to, say, an HMI board, or panel lighting/indication -- LEDs on pigtails? -- that sort of thing.

Tim

[Saimoun]

Wow, ok that is low. Then I'm really close to the limit, with 15mA for LEDs + 10mA CPU.

Interesting what you said about the GPIOs - luckily I do not do any really noisy stuff like PWM on LEDs or like (so switching signals will be only a few microamps). Looking at my design the only GPIOs connected to an external connector directly are the USB DP/DM pins, but I cannot really avoid that without using a separate MCU for USB communication.

[Siwastaja]

Without additional information, I would assume the same current rating as every other pin.

But current rating of "every other pin" is there because of the Rds_on of the output stage transistors.

No such thing with Vdd / GND, at all. Actual current rating is defined, as commented by many, by bond wires and how they exactly connect to the metal layers (power rails) in silicon. Without specifications, one can't know, but assuming it isn't any better than the weak 50-ohm-ish MOSFETs is quite pessimistic IMHO.

[T3sl4co1l]

Wow, ok that is low. Then I'm really close to the limit, with 15mA for LEDs + 10mA CPU.

Interesting what you said about the GPIOs - luckily I do not do any really noisy stuff like PWM on LEDs or like (so switching signals will be only a few microamps). Looking at my design the only GPIOs connected to an external connector directly are the USB DP/DM pins, but I cannot really avoid that without using a separate MCU for USB communication.

I don't mean like PWM and stuff, I mean it could be noise from the CPU core itself too -- anything that draws varying power within the chip.

Now, internal stuff could be down in the microvolts -- could? should? hopefully is?  I suppose with a bad enough design it could be in the mV.  But yeh, who knows, they never document stuff like that.

Mind, same is true for any other chip too, just that most have multiple power pins, dividing the ground-return impedance by a significant factor (4, 8, etc., i.e. -12, -18, ... dB).

USB is shielded so that's fine.  Well, maybe less fine if you're doing USB HID (usually unshielded?), maybe prepare for some optional filtering components if that's the case.

But current rating of "every other pin" is there because of the Rds_on of the output stage transistors.

No such thing with Vdd / GND, at all. Actual current rating is defined, as commented by many, by bond wires and how they exactly connect to the metal layers (power rails) in silicon. Without specifications, one can't know, but assuming it isn't any better than the weak 50-ohm-ish MOSFETs is quite pessimistic IMHO.

Not just Rds(on), also electromigration and stuff there too.

Pessimistic?  Sure.  I've seen devices rated for supply currents from 10mA to 200mA or more per pin (or probably much more when it comes to big CPUs' Vcore, but that's BGAs).  So then do you know which class of design they used, is it the 10mA or the 200mA kind?

Or like, if they don't say what the ESD rating is... what default should you assume, if any at all?  Supposedly, 1kV HBM is the traditional minimum.  But if they don't even say what standards they're meeting, let alone what type and level... then what?

Tim

[PCB.Wiz]

That's a lot of useful replies guys, thanks so much.

Tim going deep into details that's so great - learning a lot here.

I just checked the total current I would use which would be (absolute worst case):
* sourcing 18mA (3 sourcing LEDs)
* sinking 12mA (2 sinking LEDs)

Other details to consider when driving LEDs

The Blue and white LEDs and some others have quite high VF's so a 3.3V MCU is a bit low to drive them with a decent current defining resistor.
You can power those LEDs from 5V, (if you have that)  and drive from a 3v3 IO pin, but you would need to check the high level is 'off' enough for your needs. (faint LED effects)

The other detail to check is the VOL and VOH specs.

I see on that part, they have drive control and they describe that as 2MHz  10MHz, 50MHz,  but the VOL specs show they vary the drive strength to vary that 'speed'
For LED drive, you usually need the lowest VOL and they rate 50MHz settings at 20mA &  typ 330mV VOL  drop and 390mV VOH drop.