Author Topic: Memory model for Microcontrollers  (Read 7745 times)

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Offline eutectique

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Re: Memory model for Microcontrollers
« Reply #50 on: May 03, 2024, 04:32:07 pm »
When all variables are placed in RAM, there is a free RAM space left. That will be heap. And at the very end of RAM region there is stack. So if we magnify RAM region, we'll see something like this:


---[led_state|var2|var3|...|end|  heap--->                          <-- stack]-------


A couple of hints (for posterity):

I prefer to place heap and stack the other way round:


---[          <-- stack] [led_state|var2|var3|...|end|  heap--->                ]-------


Thus, stack will never grow to smash the variables on heap (producing mysterious bugs). Instead, it will stumble off the cliff and right into the safety net of a meaningful DataAbort handler.

Also, my stack and heap are two distinct regions in the linker script, with org and len calculated relative to each other, so that --print-memory-usage linker flag gives a nice and clear picture.
 
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Offline jnk0le

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Re: Memory model for Microcontrollers
« Reply #51 on: May 03, 2024, 04:43:32 pm »
but as far as anyone knows they are not getting money for this.

There is a lot of money involved in this kind of trolling if you consider potential use for psyops.
Either by delivering it directly or just to farm a credible accounts to be used later by "professionals" (instead of e.g. a blatant "green accounts" that suddenly have a lot to say about the rus-ua war).

And psyops term is not exclusive to the military grade ones, but even a trivial purposes like whistle marketing, or purely political.

If there is demand, there are companies selling appropriate services.
And if we are talking about commercial use, look at his 3rd photo:



neosoft - looks like company name, there are multiple similarly named companies but this one (already mentioned) explicitly mentions "AI" in whole portfolio:
https://in.linkedin.com/company/neosoft
https://www.neosofttech.com/services/artificial-intelligence-machine-learning/

neosoft-ThinkPad-X270 - default ubuntu hostname formatting: https://superuser.com/questions/734998/where-does-ubuntu-get-the-default-hostname

-W10DG - most likely inventarization number, typical in corporations

- offending company is also located in India
- reverse image search yields this thread only (unlike the "traffic light" or ebay/aliexpress one: https://irq5.io/2017/07/25/making-usbasp-chinese-clones-usable/ used here https://www.avrfreaks.net/s/topic/a5CV40000000ajRMAQ/t394567)
- what is even the purpose of photografing this, are we yet to see another GPT-question related to berkeley output from `size` program?
- he seems to be using win11 normally https://www.edaboard.com/threads/uart-communication-for-sending-integer-values.408205/ , https://www.avrfreaks.net/s/topic/a5CV40000000ajRMAQ/t394567

Also, the kittu* accounts started activity few months after the Yannic video about GPT-4chan.

If true, we are probably seeing that someone is testing something here. (like reactions, time to compromise or this is a decoy and there is higher quality bot posting from stolen accounts etc.)
« Last Edit: May 03, 2024, 04:56:41 pm by jnk0le »
 
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Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #52 on: May 03, 2024, 05:17:22 pm »
If true, we are probably seeing that someone is testing something here. (like reactions, time to compromise or this is a decoy and there is higher quality bot posting from stolen accounts etc.)

Sounds very much like so.
And the testing goes pretty well, to the point that forum admins delete messages of real users in order to defend the bot.
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Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #53 on: May 03, 2024, 05:23:00 pm »

I prefer to place heap and stack the other way round:


---[          <-- stack] [led_state|var2|var3|...|end|  heap--->                ]-------


That is a nice strategy indeed!

One may argue that the strategy when heap and stack grow towards each other is good cause gives the best RAM utilitzation, when one does not know in advance which one is going to grow more. But for an embedded application, a firmware engineer might have a pretty good idea about the limits, so the extra price to pay for safety is well worth paying.
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Offline Kittu20Topic starter

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Re: Memory model for Microcontrollers
« Reply #54 on: May 03, 2024, 05:46:15 pm »
You can think whatever you want, I won't say anything about it. I have already given my explanation. Regarding the links you shared earlier, the question I asked in the first thread, you can see the output in the terminal that i was getting after running code on my PIC micro . And in the other link, I bought the programmer, but after many attempts, I am unable to use it. Not only me many other members also complain that programmer wasn't good faced problem. I wasted my money buying the wrong programmer because I didn't have prior experience with it.
 

Offline Kittu20Topic starter

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Re: Memory model for Microcontrollers
« Reply #55 on: May 03, 2024, 05:52:20 pm »
If true, we are probably seeing that someone is testing something here. (like reactions, time to compromise or this is a decoy and there is higher quality bot posting from stolen accounts etc.)

Sounds very much like so.
And the testing goes pretty well, to the point that forum admins delete messages of real users in order to defend the bot.

I claim that you are a bot because you are posting the same message repeatedly. If you are not a bot, prove that you are not a bot



 

Offline peter-h

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Re: Memory model for Microcontrollers
« Reply #56 on: May 03, 2024, 05:53:09 pm »
Quote
a firmware engineer might have a pretty good idea about the limits

A firmware engineer won't use a heap ;)

Well, except to do a one-off malloc for some product option, never to be freed.

Or malloc+free of a block so big that fragmentation is impossible.
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Offline Kittu20Topic starter

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Re: Memory model for Microcontrollers
« Reply #57 on: May 03, 2024, 06:04:51 pm »
Since this thread has now become off-topic, I would like to ask a question. I'm noticing that some users are trolling and discouraging me, which is making me very upset. Should I leave this forum or should I ignore such people?
 

Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #58 on: May 03, 2024, 06:10:14 pm »
Quote
a firmware engineer might have a pretty good idea about the limits
A firmware engineer won't use a heap ;)
Well, except to do a one-off malloc for some product option, never to be freed.
Or malloc+free of a block so big that fragmentation is impossible.

If one needs networking / TCP/IP, then using heap is reasonable. Peter, you're the one who complained about mbedTLS being RAM hungry? :)
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Offline peter-h

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Re: Memory model for Microcontrollers
« Reply #59 on: May 03, 2024, 07:13:30 pm »
Yes, but I throw away the whole 60k block when the connection is closed, which makes it fairly safe. Fragmentation within the MbedTLS private heap is still possible but almost nobody understands MbedTLS anyway, and it seems to be pretty reliable doing what I am doing with it :)
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Offline jnk0le

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Re: Memory model for Microcontrollers
« Reply #60 on: May 03, 2024, 07:29:25 pm »
And in the other link, I bought the programmer, but after many attempts, I am unable to use it. Not only me many other members also complain that programmer wasn't good faced problem. I wasted my money buying the wrong programmer because I didn't have prior experience with it.

Those should be showing as USB HID device and work only with PROGISP software (which has expected quality, don't even bother with it).
No drivers needed if you have installed something by zadig - uninstall it. (only USBASP requires it)

Otherwise unit is defective (HW or just FW) or there is something wrong with USB LS implementation on host machine.


The best way to handle those is to immediately reprogram them into usbasp. This of course requires another working programmer and correct firmware

https://www.sciencetronics.com/greenphotons/?p=938&cpage=2 provides firmware for atmega8(L) ones. (tested on my MX-USBISP-V3.01)
https://github.com/aleh/usbisp/tree/master/bin/firmware - should have proper binaries for atmega88 ones (V4 and higher??)


EDIT: The users that have problems with them are mostly the ones expecting it to work as usbasp.

« Last Edit: May 03, 2024, 08:46:20 pm by jnk0le »
 

Offline peter-h

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Re: Memory model for Microcontrollers
« Reply #61 on: May 04, 2024, 09:56:37 pm »
On why people generate text for ChatGPT etc:

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Offline PlainName

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Re: Memory model for Microcontrollers
« Reply #62 on: May 04, 2024, 10:17:55 pm »
So they essentially want gobs of stuff to train their LLM to be the fount of all knowledge? On the one had that would be cool (if it didn't end up behind a significant paywall) - kind of like the next Google search, which was kind of like the next encyclopedia. But on the other hand it may just be masses of complete rubbish so not actually any help in making knowledge more accessible.

Copyright is a double-edged sword. Creators need an incentive to both create and share, but big corps like Disney overdo it with several lifetime's lock-in and payback. IMO, copyright should be limited to the same as patents: 20 years tops. But that's going off on a tangent... :)
 

Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #63 on: May 04, 2024, 10:24:38 pm »
Yeah, AI trains on expert content. For now, it is still easy to recognise it by a behavioral pattern.

E.g. a human pattern is to ask a question, then iterate and follow up.
Example: take a look at the "porting C++ to C" thread - https://www.eevblog.com/forum/microcontrollers/help-porting-2-functions-from-c-to-c/
Or, "starting with stm32" thread - https://www.eevblog.com/forum/microcontrollers/starting-with-stm32-(nucleo-l412kb)/

Note how much OPs iterate over the answers, trying to figure out the solution.

AI's pattern is different - it just asks the question and NEVER does any meaningful follow up. Even when many answers were given, and tons of hints. Look at this thread - not a single meaningful follow up on a on-topic answers (many of them!). Despite all the claims about "genuine interest" and so on.

But I guess AI progresses, and soon we'll see more human-like behavior, including follow-up questions, etc.
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Offline MK14

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Re: Memory model for Microcontrollers
« Reply #64 on: May 04, 2024, 10:45:20 pm »
I've investigated the OP, to a fair extent.

They do seem to be a BOT.

Fortunately, the 'owners' of the BOT, are partly open to where it comes from.

My early indications, are that considerably earlier versions, of that 'bot', were much more clearly labeled.  So, that they could be traced to, what I would prefer to call the Google AI department.

But, they instead seem to call it the Google Deep Learning (entity/department).

I can't be 100% sure, and don't want to waste lots of time researching it.

Supplying link(s) to what I found out, is not really possible in this case.  Because it involves one or more other peoples, personal information, in real life.

Also, the OP makes no sense, being a real person.  Because they seem to have several posting styles.  Varying between, poor quality English, better quality and even good quality English and coherent responses/questions.

If you want to see the actual information for yourself.  Go on a mission and find some of the OLDEST posts (anywhere), that this system of bots has made.  The questions remain all too similar.  Then look at the user and see if you can identify Google Deep Learning (obvious hints/information), from what you find.

N.B. They do seem to also use completely different user IDs, but the question(s) remain all too familiar.

Disclaimer:
If I'm wrong here, and you (the OP) are a real person and posting genuine stuff.  Then you need to consider seeking medical help, as there seem to be thousands or more, of these questions, repeated in numerous forums and similar places.  Over a very long period of time, e.g. 2007 and perhaps longer.

Also, it seems to take bits of some replies on some forums, then turn those into question(s) it puts onto completely different forums.

So the original question might be about the 'C' language.  Then someone mentions MATLAB.  Then the question changes into a MATLAB version.

I.e. Like here:
https://www.eevblog.com/forum/microcontrollers/matlab-and-c-language-in-automotive-software-development/msg5425259/#msg5425259
 

Offline MK14

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Re: Memory model for Microcontrollers
« Reply #65 on: May 04, 2024, 11:26:50 pm »
Let me give you another example.
The following, fairly recent thread, (different forum), seems to show how the possible 'BOT', changed their original question, into the one that this thread, seems to be about.

I.e. Possible so called 'machine learning'.

Also, as mentioned by someone else in this thread, notice how the 'bot' refused and ignored the comment in my link, to use GOOGLE search.

https://www.electro-tech-online.com/threads/better-use-of-function-pointers.165802/#post-1447881
« Last Edit: May 04, 2024, 11:30:26 pm by MK14 »
 

Offline IanB

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Re: Memory model for Microcontrollers
« Reply #66 on: May 04, 2024, 11:54:01 pm »
For those who'll read this thread - IMO the explanation by Nominal Animal is the most complete, I am talking about https://www.eevblog.com/forum/microcontrollers/memory-model-for-microcontrollers/msg5478241/#msg5478241
However I think it is a bit advanced. I'll take the liberty to put Nominal Animal's explanation in simple terms.

(description snipped)

This was a really nice description, thanks.

I have a follow up question:

Suppose I have some constant data, like a lookup table, for example. Since this is static, it can go into flash memory (where the code lives) and not RAM (where the variables live). However, the lookup table in the source file is data, not code. How would one go about telling the compiler to put this lookup table in its own section in flash, and not in the RAM? Would the compiler do this automatically if you declare the lookup table as static/const/readonly? Would the compiler possibly generate some initialization code that copies the data from flash to RAM on startup for ease of access? Do embedded tools typically give you control over this, and to visualize the binary layout that will be produced by the compiler/linker?
« Last Edit: May 05, 2024, 01:27:07 am by IanB »
 
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Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #67 on: May 05, 2024, 01:11:17 am »
As far as I understand, constant data goes to the .rodata section, not .data.
And usually linker scripts put .rodata on flash, right after code (.text) - exactly the way you suggested.
Example: ST's linker script for one of the H7 :

https://github.com/STMicroelectronics/cmsis_device_h7/blob/88f29645ec7e063bae3d5e58699fc541a81efac6/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld#L79-L86

The .data relocation to RAM is part of the MCU startup code. A compiler does not generate any relocation code.
Here's a snippet from the same H7 startup file:
https://github.com/STMicroelectronics/cmsis_device_h7/blob/88f29645ec7e063bae3d5e58699fc541a81efac6/Source/Templates/gcc/startup_stm32h747xx.s#L66-L86

Both linker script, and .data relocation, are explained in my guide (https://github.com/cpq/bare-metal-programming-guide), but in a more "scattered" manner.

A linker script and startup file are usually part of the device SDK. Of course anyone can modify them, but there is rarely a need to do so.
If one wants to learn how things work, one could create a really minimal working linker script, and a small C-only (no assembly) startup file.
Here's an example from the bare metal guide for STM32F429:
https://github.com/cpq/bare-metal-programming-guide/blob/main/steps/step-4-printf/link.ld - a small linker script
https://github.com/cpq/bare-metal-programming-guide/blob/main/steps/step-4-printf/startup.c - a small C-only startup file
https://github.com/cpq/bare-metal-programming-guide/tree/main/steps/step-4-printf - a complete project

I would recommend Alex's https://github.com/ataradov/mcu-starter-projects as a very nice example of minimal & functional approach to bare metal firmware implementation.
« Last Edit: May 05, 2024, 01:36:14 am by tellurium »
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Offline Kittu20Topic starter

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Re: Memory model for Microcontrollers
« Reply #68 on: May 05, 2024, 03:31:43 am »
NOTE: This message has been deleted by the forum moderator Simon for being against the forum rules and/or at the discretion of the moderator as being in the best interests of the forum community and the nature of the thread.
If you believe this to be in error, please contact the moderator involved.
An optional additional explanation is:


Thank you very much, @Simon, for deleting the post and making the right decision. If possible, please remove any unnecessary off-topic posts in the thread, close the thread, as I do not wish to continue it
 

Offline peter-h

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Re: Memory model for Microcontrollers
« Reply #69 on: May 05, 2024, 06:13:09 am »
Quote
a human pattern is to ask a question, then iterate and follow up.

Except most don't do the "follow up" bit because

- they can't be bothered
- they are working in some company which prohibits posting
- they abandoned the project
- they are working on a product and don't want to give away too much

BTW you can find out a lot about someone by googling on their forum nickname :) I regularly do this on the one I run, where the poster was quite smart but probably malicious.

Also there are sites which can identify ChatGPT output with a high probability.

Quote
constant data goes to the .rodata section, not .data.

This varies, even by version of the same CPU compiler. From my project notes:

With ARM GCC, statics are categorised thus:
int fred; goes into BSS (used to go into COMMON in GCC versions before v10)
int fred=0; goes into BSS (which by definition is zeroed by startup code)
int fred=1; goes into DATA (statics initialised to nonzero, copied to RAM at start)

I don't think anything goes into .rodata in current arm32 GCC although the original ST-supplied linkfile contains loads of code referencing it.

Another reason for freezing the compiler version on a given project, but that's another debate... I have frozen Cube IDE on 1.14.1, due to issues with the GCC tools which Cube 1.15.0 introduces. Cube itself is also broken at 1.15 - can't drive the debugger!

« Last Edit: May 05, 2024, 06:35:24 am by peter-h »
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Offline tellurium

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Re: Memory model for Microcontrollers
« Reply #70 on: May 05, 2024, 08:34:35 am »
Quote
constant data goes to the .rodata section, not .data.

This varies, even by version of the same CPU compiler. From my project notes:

With ARM GCC, statics are categorised thus:
int fred; goes into BSS (used to go into COMMON in GCC versions before v10)
int fred=0; goes into BSS (which by definition is zeroed by startup code)
int fred=1; goes into DATA (statics initialised to nonzero, copied to RAM at start)

I don't think anything goes into .rodata in current arm32 GCC although the original ST-supplied linkfile contains loads of code referencing it.

Another reason for freezing the compiler version on a given project, but that's another debate... I have frozen Cube IDE on 1.14.1, due to issues with the GCC tools which Cube 1.15.0 introduces. Cube itself is also broken at 1.15 - can't drive the debugger!

No it does not vary. "int fred" does not go to .rodata simply because it is, well, not constant. You can change it.
Try to declare `const char *message = "blah";` and see.
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Offline Nominal Animal

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Re: Memory model for Microcontrollers
« Reply #71 on: May 05, 2024, 09:57:54 am »
I'll take the liberty to put Nominal Animal's explanation in simple terms.
I didn't know what depth/complexity would be most useful, so did it what I thought would be most useful.
Having someone else do the same at a different depth/complexity is extremely useful; thanks! :-+

How would one go about telling the compiler to put this lookup table in its own section in flash, and not in the RAM?
Generally, using
    __attribute__((section ("sectionname")))
    const type varname[] = {
        values...,
    };

With older AVRs with separate Flash and RAM address spaces and separate machine instructions to access them, we have __flash qualifier that causes the (C only for GCC, C or C++ for Clang>=13) to put it in the .progmem.data section, so to use a different section, you use an alias:
    __attribute__((section ("sectionname")))
    static const type internal_varname[] = {
        values...,
    };
    extern __attribute__((alias ("internal_varname")))
    __flash const type varname[ sizeof internal_varname / sizeof internal_varname[0] ];
Because of the __flash qualifier, accesses to varname will use the LPM instruction.
For compatibility, it is best to use sectionnames that begin with .progmem. .

Other compilation units (source files compiled to different object files) accessing the array should use prototype
    extern __flash const type varname[size-if-known];
where size-if-known is the number of elements, or omitted if unknown.

(The reason this alias trick works correctly is that the __flash attribute tells the compiler to generate the correct code (LPM et cetera, instead of LDS et cetera); but symbol references use only the name (without any section references).  Thus, similar tricks will work in all compilers having such qualifiers, using ELF object files and symbol aliasing.)

The source code generated will be similar to
            .section bar,"aw",@progbits
            .type array, @object
            .size array, size-in-bytes
    internal_varname:
            array contents
    .global varname
            .set varname,internal_varname
generating the expected machine code and object files; internal_varname will be a local symbol, and not accessible from other compilation units.

Another option is to use only the __flash qualifier, and compile the lookup table to a separate object file, then change the section name using e.g. avr-objcopy --rename-section .progmem.data .progmem.name lookuptable.o .

Even older versions of GCC (I have 5.3.0, for example) generate acceptable code for AVRs, but for Clang, you'll want version 16 or later.

In general, the __attribute__((section (sectionname))) used with a function or data object (variable or constant) picks up the "type" of the section from what it is used with for the assembler, so technically setting a section affects both the function or data object it is used with, and the section declaration itself.  GCC and Clang linker scripts, however, use only the section name, so using common prefixes with '.' separators makes writing linker scripts easier.  Standard linker scripts, for example, tend to consider all sections starting with .text. as just another .text section, so with suitable standard prefix section names, one won't need to modify the linker scripts at all.  (The __flash or equivalent qualifier is needed to tell the compiler which instructions can be used to access the variable or data object.  The AVR io attribute works in a similar way, but for register and I/O bit manipulation.)

Would the compiler do this automatically if you declare the lookup table as static/const/readonly?
For certain targets (having a single Flash + RAM address space) using certain compiler options (-fdata-sections to put each data variable or object into a separate segment) and linker scripts, yes.

For example, ARM Cortex-M targets using standard linker scripts and -fdata-sections GCC or Clang compiler option would do this.

Would the compiler possibly generate some initialization code that copies the data from flash to RAM on startup for ease of access?
No, that is done by the boot loader or initialization code, which is also responsible for setting up stack; and on more complex microcontrollers, sets up clock sources, trains DRAM, and so on.

Do embedded tools typically give you control over this, and to visualize the binary layout that will be produced by the compiler/linker?
Yes.  There are two separate cases: one where the boot loader is separate, possibly in a reserved Flash section, and does all the initialization; and the other where there is no bootloader per se (and the system cannot update its own firmware, it is done using external tools).

In the first case, the boot loader code base is separate.  It gives some promises –– minimally in the form of the linker script specifying the memory ranges available to the application part, and the address of the symbol that is executed whenever the boot loader has done ––, which should be documented somewhere, especially if it also provides additional functions in Flash one can utilize, but the linker script does describe the minimum details and the layout.

In the second case, the initialization code is linked with the application part, so the final link map (you can obtain from linker tools) will describe the full firmware image.  In this case too the linker script will describe the binary layout.  (It varies whether the locations of memory-mapped peripherals are defined in the linker script, accessed via fixed-address pointers in the source code, or via fixed-address C/C++ extension attributes in the source code.  The last one is common in older Harvard architectures with multiple address spaces, for example when bit access instructions are limited to a small I/O address range.  So, the linker script may not describe how all peripherals are accessed, even if in the same address space; for those, you need to examine the source code.)
 
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Offline PlainName

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Re: Memory model for Microcontrollers
« Reply #72 on: May 05, 2024, 10:39:25 am »
Suppose I have some constant data, [...] How would one go about telling the compiler to put this lookup table in its own section in flash, and not in the RAM? Would the compiler do this automatically if you declare the lookup table as static/const/readonly?

Strictly, the compiler plays not part other than to label things. The linker is the bit that places everything in the appropriate parts of the memory map. Nowadays it's unusual to think about the linker because the compiler or IDE will run it automatically, and the IDE vendor provides suitable default directives. If you check some embedded project source there will no doubt be a .ld file, which tells the linker what to place in which sections and where they locate in absolute memory.

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Would the compiler possibly generate some initialization code that copies the data from flash to RAM on startup for ease of access?

Not really, but... The compiler just compiles code. There will be a startup file which does the system initialisation, from initial boot to setting up memory (if necessary), copying initialised data, etc., then chainging to main().

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Do embedded tools typically give you control over this, and to visualize the binary layout that will be produced by the compiler/linker?
[/quote]

More so than desktop or phone apps, but the IDE may not make it easy. Can't offhand think of one that makes it easy to visualize what the result will look like - see the attached linker files for PIC32 and STM32 projects, for example. A user either won't mess with these, ever, or will play around at the start of the project and then be done with it.

Attached are STM32 and PIC32 linker files, and typical STM32 startup code. I added the .txt extension for the forum to accept them. If you browse any embedded project you have you should find something similar.

edit: nominal beat me to it, more coherently. But the attachments may still be useful to scare you off dealing with 'em  :)
« Last Edit: May 05, 2024, 10:41:32 am by PlainName »
 

Offline mikeselectricstuff

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Re: Memory model for Microcontrollers
« Reply #73 on: May 05, 2024, 10:47:50 am »
Quote
How would one go about telling the compiler to put this lookup table in its own section in flash, and not in the RAM?
Generally, using
    __attribute__((section ("sectionname")))
    const type varname[] = {
        values...,
    };
Any decent compile/link ecosystem should by default put const data in flash unless explicitly told to do otherwise - as mentioned there are sometimes reasons to do otherwise, like harvard architectures that may have a speed penalty, or where flash and RAM have different access speeds, but these should be something that has to be explicitly requested.   
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Offline nctnico

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Re: Memory model for Microcontrollers
« Reply #74 on: May 05, 2024, 11:05:05 am »
Quote
How would one go about telling the compiler to put this lookup table in its own section in flash, and not in the RAM?
Generally, using
    __attribute__((section ("sectionname")))
    const type varname[] = {
        values...,
    };
Any decent compile/link ecosystem should by default put const data in flash unless explicitly told to do otherwise - as mentioned there are sometimes reasons to do otherwise, like harvard architectures that may have a speed penalty, or where flash and RAM have different access speeds, but these should be something that has to be explicitly requested.
I agree. Using sections is a complicated way versus simply using const if the goal is to have data in flash.

Often there are a whole bunch of sections in the linker descriptor file which doesn't make making changes easy. And the linker descriptor file will vary per target / microcontroller type so using sections doesn't make code very portable either (besides needing to document the non-standard sections). So in general I'd advise against using sections unless there really is no alternative way.
« Last Edit: May 05, 2024, 11:07:19 am by nctnico »
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