Author Topic: Memory model for Microcontrollers  (Read 10142 times)

0 Members and 1 Guest are viewing this topic.

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #100 on: May 06, 2024, 08:47:39 am »
Quote
So, when we go to the following thread:
https://forum.allaboutcircuits.com/threads/biometric-system.192026/#post-1801070

Having followed that link, and the subsequent link, I don't find the questions indicate what you believe to be the case. The thing about the box vs sleeve is that it's not obvious what it is or should be called - I wouldn't call it a sleeve (it's cardboard, not paper). And the 'card below' is credit-card sized but isn't a credit card (since it has a fingerprint reader embedded, apparently).

Here is the picture:



I argue/suggest, that a real human (Adult) Intern, would readily and immediately know what the sleeve is in the picture.

Link in question:
https://www.biometricupdate.com/201805/mastercards-remote-enrollment-solution-for-biometric-payment-cards-developed-with-idex

But, I do agree, that the biometric (sensor) bit, is NOT obvious, to everyone.
« Last Edit: May 06, 2024, 08:54:19 am by MK14 »
 

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #101 on: May 06, 2024, 09:09:03 am »
Quote
So, when we go to the following thread:
https://forum.allaboutcircuits.com/threads/biometric-system.192026/#post-1801070

Having followed that link, and the subsequent link, I don't find the questions indicate what you believe to be the case. The thing about the box vs sleeve is that it's not obvious what it is or should be called - I wouldn't call it a sleeve (it's cardboard, not paper). And the 'card below' is credit-card sized but isn't a credit card (since it has a fingerprint reader embedded, apparently).

As regards your criticisms of the 'credit card', I agree with you.  Because, biometric sensors, on credit cards, is not that obvious.

But, the way that Kittu20, talks and asks about credit cards, complete with a picture of one.  Makes it sound like, they (Kittu20), don't really know or understand about credit cards.

As would be expected, from some kind of AI/machine-learning/deep-learning entity, which has never touched or seen a credit card, in real life.  Hence the confusion and strange/weird questions, from Kittu20.

Excluding somewhat obvious exceptions, such as they live in an underground cult, in the middle of know-where, and never meet or interact with real people.
 

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #102 on: May 06, 2024, 09:25:47 am »
Does my question not make sense? I see that many experts also have doubts, which they are clarifying in this thread by asking other members. Then, as an intern, why can't I have doubts?

Do you now know what a 'short short' is?

https://forum.allaboutcircuits.com/threads/rules-of-c-language-are-very-confusing.189740/

Quote
All About Circuits
Thread Starter
Kittu20

    Joined Oct 12, 2022

    479

Oct 15, 2022

    #1

I find the rules of c language are very confusing

This is a valid statement in c language
Code:

long long count;

I don't understand why following statement is invalid in c language
Code:

short short count;

please can someone explain what is the reason behind this
 

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 6442
  • Country: fi
    • My home page and email address
Re: Memory model for Microcontrollers
« Reply #103 on: May 06, 2024, 09:32:34 am »
What I was curious about is when you target an embedded platform, you might also have initialization code automatically added to your binary via the platform SDK, and that this code would do whatever is necessary on the platform you are targeting to set things up before entering your code.
Note that the linker script can always include specific object files (that do not need to be mentioned in compiler or linker command line options).

Thus, the linker script is the first place you should look at, to find out what kind of initialization or support code a build toolchain will include, and what kind of memory layout will be generated (unless ASLR and dynamic linking is used).

The C runtime (some *crt*.o files) is just so common that compiler default linker scripts have them baked in for fully-hosted environments (i.e., code running under a fully-featured operating system, with the standard C library available).

This is also the reason why I believe all embedded programmers should learn to read (and to a lesser degree, write) GCC/Binutils/Clang linker scripts.  I did it by reading the linker script documentation while examining existing linker scripts.  If you have ever used Awk or its variants, you'll find the basic idea of operation familiar; otherwise, think of linker scripts as recipes, or rules, the linker needs to follow.  If you don't have any linker scripts at hand, look at the various Arduino support cores, they have plenty of them.

(It would also be very useful to understand the difference between 'fully-hosted' and 'freestanding' C and C++.  Freestanding C is pretty well defined in the standards, while for C++ it is 'implementation defined'; but mainly it deals with the difference in what features are available.  Some header files like <stddef.h>, <stdint.h>, <stdarg.h>, <stdbool.h>, <stdalign.h>, <stdnoreturn.h>, <limits.h>, <iso646.h>, and <float.h> are provided by the compiler, so they and all they expose are always available (if at all; some of those depend on the C version used).  The (rest of) standard C library is only available in hosted environments.  For linking, it also means C runtime support (*crt*.o) is not included in builds based on freestanding C.)

I argue/suggest, that a real human (Adult) Intern, would readily and immediately know what the sleeve is in the picture.
I'm an adult but not an intern who has had that brand credit card for a couple of decades, but didn't know what the heck the purpose of that sleeve is: I've never seen those before.  (I'm also rather skeptical about biometrics here: if robbed, I'd rather prefer to keep my fingertips, than have the robbers take those too.  Obligatory XKCD: 538.)

It seems to me that if Kittu20 is a real human being only using LLM to help them with their English output (as opposed to training one and/or acting as an intermediary to one), it would be a good idea to stop: the way LLMs are used now –– some claim already about half of web traffic is bots (although only a small fraction use LLMs) –– means that broken English is better accepted in technical discussions than LLM/bot use is.  (Even just a week ago I thought it'd be okay to use LLMs for helping with foreign language output; now I do not think so anymore.)
« Last Edit: May 06, 2024, 09:37:21 am by Nominal Animal »
 
The following users thanked this post: MK14

Offline peter-h

  • Super Contributor
  • ***
  • Posts: 3758
  • Country: gb
  • Doing electronics since the 1960s...
Re: Memory model for Microcontrollers
« Reply #104 on: May 06, 2024, 09:47:12 am »
Quote
Note that the linker script can always include specific object files (that do not need to be mentioned in compiler or linker command line options).

This is a great observation. After some of the posts here I went to look in Cube, as a little exercise, to see where the order of the program modules is set up, and could not find it. Of course it is in the linkfile... You start with specific modules e.g. vectors.o, then startup.o and then you collect up all the other stuff with *.o

It doesn't actually matter so long as vectors.o is the first one.

There is a vast amount of obscure config in Cube for the libraries to be used. Loads of ways to get burnt by changing it accidentally.
Z80 Z180 Z280 Z8 S8 8031 8051 H8/300 H8/500 80x86 90S1200 32F417
 

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 6442
  • Country: fi
    • My home page and email address
Re: Memory model for Microcontrollers
« Reply #105 on: May 06, 2024, 10:38:10 am »
I believe that trying to write a single linker script to cater for multiple use cases will result in an ugly, unmaintainable result.

The best linker scripts I've seen target a specific variant and use case of a board.
Adding support for a new MCU or board is then easy, as one starts from the most similar existing one, saves it under a new name related to the MCU and/or board, and does the required modifications.

Early development with multiple targets is more work, because you have to carefully copy the changes across all targets' linker scripts and keep them "in sync" with respect to changes; but, when they finally stabilize, it gets much easier and is worth it.

If you use a separate linker scripts for production and development, you can use the exact same code base, even exact same object files without recompilation: just discard any debugging-related information.  You do need to use dedicated sections for the debugging stuff; I use preprocessor macros with descriptive names for the section definitions.  You can use the ELF tools (objdump/readelf) to examine relocation records, to see if any outside the debugging-related sections refer to debugging information, to ensure nothing ever tries to access the removed data or functions.  (Because that is a "If there are any, it is a failure" type check, it is quite simple and robust.  Also, the exact same mechanism is used internally with -ffunction-sections -fdata-sections -Wl,--gc-sections options to prune out unused data and functions, so this is a commonly trusted mechanism already; not a "hack".)

Consider, for example, writing a simple variable-accessing interface for use during testing.  You use the structure-in-a-dedicated-section to describe each variable (type, pointer to, name, and possibly valid range), and a simple parser to query and set them at run time via some serial interface.  You separate its initialization and operation to separate functions in a debugging section, and create a weak non-debug initialization function stub that just returns.  The normal initialization code only calls that initialization function; the debug one if it is linked in, the do-nothing stub if the debug one is omitted.  (This is how weak ELF symbols work; they're extensively used in library code to allow application code to override library functions just by writing a non-weak function with the same signature.)
The benefit is that at run time, depending on which sections are included and which dropped, only the initialization function call target changes, and there are no other non-debug code changes in the firmware between instrumented and production builds.  Much better than compiling instrumented and production builds separately, if machine-code level examination is needed/useful.  Ordinary devices and hobbyists don't care, though – except for oddball paranoid uncle bumbleϝucks like myself.
 

Offline eutectique

  • Frequent Contributor
  • **
  • Posts: 415
  • Country: be
Re: Memory model for Microcontrollers
« Reply #106 on: May 06, 2024, 11:05:39 am »
Quote
All About Circuits
Thread Starter
Kittu20

    Joined Oct 12, 2022

    479

Oct 15, 2022

This is a valid statement in c language

long long count;

I don't understand why following statement is invalid in c language

short short count;

please can someone explain what is the reason behind this



 
The following users thanked this post: MK14, tellurium

Online PlainName

  • Super Contributor
  • ***
  • Posts: 6972
  • Country: va
Re: Memory model for Microcontrollers
« Reply #107 on: May 06, 2024, 12:46:33 pm »
I argue/suggest, that a real human (Adult) Intern, would readily and immediately know what the sleeve is in the picture.

What's with the 'human (Adult) Intern' stuff? Too many variable there :)

I'm an adult (though not an intern) and English is my native language, but if you asked me what that thing is without benefit of this thread, I wouldn't have called it a sleeve. Actually, I'm not sure what I would have called it, but 'sleeve' is not the first thing to pop into my head.

I think part of the reason for that is because it doesn't go the full length of the card. I would be thinking of some term related to 'slot'.

Anyway, the gist is that I agree that there is something peculiar - it strikes me that some of the questions wouldn't be asked by someone clearly as versed in the arts as previous questions suggested. A little like a teacher running a test (which would tie in with generating LLM fodder). But the examples you gave there are not, IMO, definitive. I've seen far more likely ones from actual humans on here, and those have been English-speaking humans at that!

I'm intrigued that no-one has wondered what 'intern' means in all this. A student at college? Someone working for free for the experience? Graduate on his first job?
 
The following users thanked this post: MK14

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #108 on: May 06, 2024, 02:57:55 pm »
What's with the 'human (Adult) Intern' stuff? Too many variable there :)
...
...cut...
...
I'm intrigued that no-one has wondered what 'intern' means in all this. A student at college? Someone working for free for the experience? Graduate on his first job?

True, there is quite a lot of scope for intern, to mean a wide range of things.

I also agree that your posts and other(s), suggesting that it is NOT so obvious, to know what some of the things I posted in the thread, actually are (at least to EVERYONE), is a valid point/contradiction to my (AI/Deep-learning) narrative.

I have managed to find the following, which seems to be the same user.  But, their thread and posts, seem to be much more like a real human.

https://www.avrfreaks.net/s/topic/a5C3l000000UkUVEA0/t191795?page=1

Because, they seem to show detailed, and clear photographs of hand drawn circuit(s) and real physical electronics in use, by an upcoming hobbyist.

I suppose, anyone round the world, who is reading technical books, or even internet technical articles.  When they have the slightest misunderstanding (e.g. why are PNP as opposed to, NPN transistors, used in circuits, sometimes).

Could create hundreds of forum accounts, in different websites, and over a period of time. Put those questions, in them.

Eventually amassing a huge number of threads/questions, all over the place.
« Last Edit: May 06, 2024, 02:59:46 pm by MK14 »
 

Online IanB

  • Super Contributor
  • ***
  • Posts: 11972
  • Country: us
Re: Memory model for Microcontrollers
« Reply #109 on: May 06, 2024, 03:19:13 pm »
I'm an adult (though not an intern) and English is my native language, but if you asked me what that thing is without benefit of this thread, I wouldn't have called it a sleeve. Actually, I'm not sure what I would have called it, but 'sleeve' is not the first thing to pop into my head.

I think part of the reason for that is because it doesn't go the full length of the card. I would be thinking of some term related to 'slot'.

It's a card reader, surely?

If you go shopping with your chip-enabled credit or debit card, you push it into the card slot, and it goes about half way in. This is normal.

Many people (especially in the UK) may have a card reader device from their bank for online banking. This also has a slot that accepts about half the length of the card (this is all that is needed to read the chip).

When I look at the photo above, it seems obvious that it is a credit card. Without reading the article, what comes to mind is a "chip and fingerprint" security device on a card, as an alternative to the usual "chip and pin" security. Naturally, the fingerprint reader part needs to be exposed so you can put your finger on it, while the chip needs to be inside the machine, so it can read the data off it.

 
The following users thanked this post: MK14

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #110 on: May 06, 2024, 03:22:47 pm »


Thanks, that's funny (and interesting, in its own way, how distinguished people, react, to such questions).

I've watched it twice, and others now, or closely related, including the first part, of that video series.
 

Online PlainName

  • Super Contributor
  • ***
  • Posts: 6972
  • Country: va
Re: Memory model for Microcontrollers
« Reply #111 on: May 06, 2024, 03:30:38 pm »
I'm an adult (though not an intern) and English is my native language, but if you asked me what that thing is without benefit of this thread, I wouldn't have called it a sleeve. Actually, I'm not sure what I would have called it, but 'sleeve' is not the first thing to pop into my head.

I think part of the reason for that is because it doesn't go the full length of the card. I would be thinking of some term related to 'slot'.

It's a card reader, surely?

If you go shopping with your chip-enabled credit or debit card, you push it into the card slot, and it goes about half way in. This is normal.

It's not a card reader I've ever seen before: too thin, and no display or keypad. So whilst it likely is a card reader, I wouldn't have described it as one on first sight. For all I know it might've been a card holder that sticks on something and you use it to park your card.
 

Offline Kittu20Topic starter

  • Regular Contributor
  • *
  • Posts: 115
  • Country: in
Re: Memory model for Microcontrollers
« Reply #112 on: May 06, 2024, 03:46:19 pm »
To those who think I'm a bot, thank you  I am bot who draws circuit diagrams by hand, purchases electronic components, connects them on a breadboard, solder components onto PCBs, tests circuits using a multimeter, writes and compiles code, and views results in a terminal. I know that if I ask any questions on this forum, I may continue to be trolled. Therefore, perhaps I should refrain from participating in this forum
 
The following users thanked this post: MK14

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #113 on: May 06, 2024, 03:52:57 pm »
To those who think I'm a bot, thank you  I am bot who draws circuit diagrams by hand, purchases electronic components, connects them on a breadboard, solder components onto PCBs, tests circuits using a multimeter, writes and compiles code, and views results in a terminal. I know that if I ask any questions on this forum, I may continue to be trolled. Therefore, perhaps I should refrain from participating in this forum

Trolling, would surely mean, that the people involved were doing it on purpose.

But, if it was being done, because of mistakes and/or misunderstandings, that would be different.
« Last Edit: May 06, 2024, 03:58:19 pm by MK14 »
 

Offline nctnico

  • Super Contributor
  • ***
  • Posts: 27232
  • Country: nl
    • NCT Developments
Re: Memory model for Microcontrollers
« Reply #114 on: May 06, 2024, 04:41:02 pm »
To those who think I'm a bot, thank you  I am bot who draws circuit diagrams by hand, purchases electronic components, connects them on a breadboard, solder components onto PCBs, tests circuits using a multimeter, writes and compiles code, and views results in a terminal. I know that if I ask any questions on this forum, I may continue to be trolled. Therefore, perhaps I should refrain from participating in this forum
I'd like to recommend you to buy this book: https://www.oreilly.com/library/view/making-embedded-systems/9781098151539/ It is not super expensive and well worth the money. I can highly recommend it to anyone wanting to venture into working with microcontrollers.

This book answers a lot (if not all) of the questions you have in a much more structured way compared to gathering bits & pieces from a forum.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 
The following users thanked this post: MK14

Offline MK14

  • Super Contributor
  • ***
  • Posts: 4586
  • Country: gb
Re: Memory model for Microcontrollers
« Reply #115 on: May 06, 2024, 05:34:15 pm »
To those who think I'm a bot, thank you  I am bot who draws circuit diagrams by hand, purchases electronic components, connects them on a breadboard, solder components onto PCBs, tests circuits using a multimeter, writes and compiles code, and views results in a terminal. I know that if I ask any questions on this forum, I may continue to be trolled. Therefore, perhaps I should refrain from participating in this forum

I'm SORRY, if I've caused any offense or annoyance.

Unfortunately, this forum seems to get lots of 'attacks' from bots and similar, these days.

I'd suggest, anyone using ChatGPT, as part or all of their post.  Should carefully and clearly label the content as such.  Otherwise, it can make the poster look like a bot.

Second excuse:
I keep on seeing, the following forum warning message, currently (which reminds me of spammers, old style bots and ChatGPT related bots etc):
Quote
News:

WARNING: We have had a huge uptick in the number of hijacked accounts on the forum.
Security on the forum has NOT been compromised, it's because spammers have gotten a stolen credentials list, and people reuse passwords.
Please DON'T REUSE PASSWORDS, and change your pasword if you think you have been compromised.
And if you get an email that someone has tried to log into your forum account, if means your details have been compromised elsewhere and other accounts you have on other sites are at risk.
 

Offline peter-h

  • Super Contributor
  • ***
  • Posts: 3758
  • Country: gb
  • Doing electronics since the 1960s...
Re: Memory model for Microcontrollers
« Reply #116 on: May 06, 2024, 06:52:29 pm »
I am afraid that all forum mods are struggling with ChatGPT - whether it is humans making generic-question posts to generate potential text for "AI" (as this guy seems to be doing) or people using ChatGPT to generate text for posting (possibly because they can't speak any English and ChatGPT is a bit better than google translate).

Fortunately, for now, ChatGPT produces fairly obvious output. Bland, sickly-sweet, devoid of any personal "colour". But this will change.

Dealing with this is a part of my job and FWIW I start with looking at the original poster signup parameters. I won't list them all openly but start with comparing the declared country (no country selected -> ban) with the IP country. If the two are say the USA and India, then ban. Look at activity (yes admins can see it all) and humans with an actual interest will have been doing the right sort of searches before the signup. Etc. The problem is doing this on a big forum, say 100 signups a day... a lot can be automated (like the IP comparison, but that needs to be done carefully).
Z80 Z180 Z280 Z8 S8 8031 8051 H8/300 H8/500 80x86 90S1200 32F417
 
The following users thanked this post: MK14

Online jnk0le

  • Regular Contributor
  • *
  • Posts: 54
  • Country: pl
Re: Memory model for Microcontrollers
« Reply #117 on: May 06, 2024, 07:32:47 pm »

I have managed to find the following, which seems to be the same user.  But, their thread and posts, seem to be much more like a real human.

https://www.avrfreaks.net/s/topic/a5C3l000000UkUVEA0/t191795?page=1



In that thread this dongle does enumerate as USBHID, later under "libusb-win32 devices", after which PROGISP was tried and failed.
At this stage uninstalling the libusb driver should make the PROGISP detect the probe. (may need a reconnection)

About a year later:
https://www.avrfreaks.net/s/topic/a5CV40000000ajRMAQ/t394567

It suddenly doesn't appear in dev manager at all.

Assuming this is the same probe, considering the "wasted money" comments. He could be trying to reprogram it to usbasp (as indicated by linked website), but with the wrong firmware.
Then the "translation" process has cut out the most important part of why it doesn't show up in dev manager.
« Last Edit: May 06, 2024, 11:06:26 pm by jnk0le »
 
The following users thanked this post: MK14

Offline westfw

  • Super Contributor
  • ***
  • Posts: 4225
  • Country: us
Re: Memory model for Microcontrollers
« Reply #118 on: May 07, 2024, 05:34:02 am »
Quote
I came across this link https://www.geeksforgeeks.org/memory-layout-of-c-program/amp/ explaining the C memory layout and how variables are stored in memory sections. The example used here involves a PC.

I'm curious to know if this memory model is also applicable to microcontrollers like 8051, PIC, AVR, and ARM. Have you used this c memory model for these microcontrollers?


On the negative side, there is more discussion here on the nature and motivation of the poster than there is on either answering or clarifying the question (on both the OP's side AND the other forum members.)

If either side would just SHUT UP about whether this is some sort of ChatGPT experiment, perhaps there would be enough useful content here for ... OTHER people to learn something (maybe here, maybe through "AIs" - what do you care if your answers get filtered through algorithms before it gets sent to the next person who asks a question?  I doubt whether many of you are using your EEVBlog forum posts in the "publications" section of your resume...

So, with that in mind...
  • The "memory model" of having text, data, bss, stack, and heap is a C language thing.  The exact implementation varies.
  • As a "C language thing", the memory model is very much applicable to microconrollers.
  • Yes, it's used on PIC, AVR, and ARM, and probably 8051.
  • Yes, I've used it on both AVR and ARM (and also embedded x86, 68k, PPC, and MIPS.)
  • The referenced web page does NOT really "involve a (modern) PC" when it comes to the details of the locations and growth direction of the various memory areas.  With the 64bit address space now commonly available, a PC program probably picks some ridiculously large part of the address space for each piece, and then uses the OS and MMU/Pager to attach pieces of that address space to real memory as needed.  eg Code at 0x1000000000000, Data at 0x2000000000000000, Heap at 0x73adf00000000000, Stack at 0x88deadbee0000000.  (Note the weird addresses for Heap and Stack.  It's a modern feature to randomize those addresses for security reasons.  And the program doesn't need Stack or Heap addresses till runtime.)  Also, it leaves out the now-common "read only data" section, which is important on PC-like systems for security purposes, and on microcontrollers so that constant data can be placed in flash.
  • Exact implementations vary.  For example, some compilers use a separate data stack and return stack (I think this is probably required for PIC and 8051, but there are AVR compilers that do it as well.)
  • Hardware varies.  On many microcontrollers, flash and RAM are not contiguous, or even in the same address space.  And I've even used systems where the stack grows upward.  A non-readable return stack is pretty common (that's why "two stacks" on a PIC.)
  • Optimizations vary.  I believe that implementing the data stack on a PIC is sufficiently expensive that it is a compiler option to allocate function-local data (which would normally be on a stack) globally, which is pretty easy as long as you haven't done any recursion.
  • Implementation and management details of the Heap are especially variable.  Systems I've used have kept careful track of free/malloc calls - which task did them, from which PC, a queue of the last N mallocs and frees, etc  (I think it's a law: "in any large system, the complexity of malloc/free will increase until you also need to implement some sort of "lighter weight memory allocator."")
  • The usual suspects have posted a bunch of useful information (THANK YOU nctnico, nominalAnimal, brucehoult!) about how a lot of the memory layout is actually under developer control.  (but I'd claim that the "model" remains the same.)

If Kittu20 needs additional explanation or details, they need to be more explicit about telling us exactly what parts they don't understand, or what additional information they need, or how they are confused.  (that this hasn't been forthcoming is ... one of the problems in this thread.)

Meanwhile, there are signs that OTHER people (including myself) are learning stuff from the technical-content posts in this thread, which is a good thing.

[/list]
 
The following users thanked this post: MK14, Nominal Animal, Tation

Offline westfw

  • Super Contributor
  • ***
  • Posts: 4225
  • Country: us
Re: Memory model for Microcontrollers
« Reply #119 on: May 07, 2024, 06:12:41 am »
Quote
The "memory model" of having text, data, bss, stack, and heap is a C language thing.
Hmm. I should clarify that AFAIK, this model originated in C (on the PDP11), or perhaps one of the C predecessors (Algol?  BCPL?   The Fortran compilers I used didn't have a stack.)  However, it's a pretty useful and workable memory model that is now used for many other languages as well.
 

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 6442
  • Country: fi
    • My home page and email address
Re: Memory model for Microcontrollers
« Reply #120 on: May 07, 2024, 07:04:02 am »
but I'd claim that the "model" remains the same.
Yes.  It can be extended by additional sections if using ELF-based toolchains, and its layout is controllable by the linker script or linker options, but the underlying idea/model –– and purpose –– remains the same.

Thinking about the ways you can maximally utilize your Flash and RAM is the same thing as thinking about how to best use the "model".

(I personally am a big proponent of using those additional sections, to both provide useful build-time and run-time features, but also making the source code more maintainable in the long term.  I use them on all sorts of architectures, from small AVR firmware code, to fully featured x86-64 Linux applications.)

Arduino environment is not the best example of how to utilize the "model", especially on older AVRs.  The design of the "model" in Arduino environment is a compromise: it was heavily limited by the choice of the GNU g++ compiler, which cannot handle the separate address spaces and machine instructions used to access Flash and RAM, for technical reasons.  The GNU gcc compiler can, but it would have limited the Arduino sketches to freestanding C, instead of freestanding C++ which they chose to use.  (Clang can, in both C and C++, but for AVRs you'll want version 16 or later, which was released in late 2023; so it wasn't a possible choice for Arduino, until very very recently.)

Fortunately, for ARM Cortex-M cores and many others, those with a single address space for Flash and RAM, the "model" does not have such low-level restrictions.  Even later AVRs have such a unified address space, because it makes development for them in C and C++ so much easier.

Quote
The "memory model" of having text, data, bss, stack, and heap is a C language thing.
Hmm. I should clarify that AFAIK, this model originated in C (on the PDP11), or perhaps one of the C predecessors (Algol?  BCPL?   The Fortran compilers I used didn't have a stack.)  However, it's a pretty useful and workable memory model that is now used for many other languages as well.
If we ignore small differences like whether there is a stack, one stack for return addresses and data, a return address stack only, or separate stacks for return addresses and function local variables, I do believe the base model originates in the very first true operating systems that allowed executing programs and returning back to initial system state afterwards; i.e. not simply grabbing the hardware, but "playing nice" with others.

I mean, surely there were (similar) implementations before that, too, but at that point in time, such a "model" became mandatory for tracking the resources a program would use, and to provide interfaces for such programs to request and release data memory from the operating system.  (I do believe that for predecessors to ANSI C, the first such interfaces used brk() or sbrk() instead of malloc()/free().)

Simply put, dividing the memory address space needed into code, uninitialized data, initialized data, and optionally stack, is the minimum requirement for such tracking and management.  It also turns out that even when developing embedded firmware or kernels, such divisions (and more detailed subdivisions and additions) are useful and effective for a number of purposes, so it just stuck.

In a very real sense, it is the minimum common denominator among machine code memory use organization.

I just recently saw someone making the argument that C has come to define the de facto standard ABI for pretty much all other programming languages.
ABI, or application binary interface, is a different thing, to the "model" discussed here.  ABI describes how data is passed between different programs, or between an "application" and a "kernel" or "library".

C basically requires a calling convention where one or more variables can be passed to the callee (called code) by value (i.e., changes done in the callee are not visible to the caller), and the callee returns a single variable.
The argument is that some ABIs are designed to optimize this and this only, with other details like which registers the callee is required to keep unchanged, and which registers it can modify ("clobber" is the term used!) based on C; and this yields suboptimal results.

I agree.  C is not the do-all, be-all of programming languages, and although it is currently the easiest for other programming languages to use for binding –– interfacing to code written in other programming languages ––, it should not be used as the only design criteria or guide.

Fortunately, compilers can support more than one ABI at the same time, even on the same hardware architecture.  For example, the embedded ARM Cortex-M ABI –– arm-none-eabi or arm-none-eabihf in ELFy terms –– is different to the ABI used in Linux (arm-linux-eabi or arm-linux-eabihf).  (The hf at end indicates hardware floating point support.)

32-bit Intel/AMD x86 and 64-bit x86-64 has several different ABIs, originating from different operating systems.
If you are familiar with Windows code, then that's exactly what e.g. fastcall, cdecl etc. do on a per-function basis, although they only modify the calling convention part of the ABI.

Linux happens to use the SysV ABI on both x86 and x86-64.  You can find its description for example here.  The x86-64 System V ABI has one peculiarity I've found is very nice, even in C, because it was not designed solely for C in mind: it supports returning two different (integer or pointer) variables in registers (as well as passing up to six (integer or pointer) variables in registers).  It means that I can do e.g.
Code: [Select]
typedef struct {
    int64_t  value;
    int64_t  status;
} i64_value_status;

i64_value_status  my_function(int64_t a, int64_t b, void *cptr, long d, void *eptr, uint64_t f);
and all parameters and the result value and status will be passed in registers, without going through the "slow" stack.

Thus, once again, the ABI thing is not really a technical question, but a human one: how does one agree upon a good ABI?  Using C as your only yardstick is not a good way.  But, humans being humans, when your only tool is a hammer, all problems look like nails; and many humans do tend to stick to a single tool.
« Last Edit: May 07, 2024, 07:09:18 am by Nominal Animal »
 

Offline Tation

  • Regular Contributor
  • *
  • Posts: 60
  • Country: pt
Re: Memory model for Microcontrollers
« Reply #121 on: May 07, 2024, 08:24:55 am »
Linux happens to use the SysV ABI on both x86 and x86-64.  You can find its description for example here.  The x86-64 System V ABI has one peculiarity I've found is very nice, even in C, because it was not designed solely for C in mind: it supports returning two different (integer or pointer) variables in registers (as well as passing up to six (integer or pointer) variables in registers).  It means that I can do e.g.
Code: [Select]
typedef struct {
    int64_t  value;
    int64_t  status;
} i64_value_status;

i64_value_status  my_function(int64_t a, int64_t b, void *cptr, long d, void *eptr, uint64_t f);
and all parameters and the result value and status will be passed in registers, without going through the "slow" stack.

ARM's AAPCS also states a parameter and return value passing mechanism that uses registers and, if not enough space on registers, then uses the stack or a memory buffer. The mechanism uses registers R0 thru R3 allowing the passing of up to 4 parameters or a vector up to 128 bits.

The AAPCS even states that:
Quote
It should be noted that the above algorithm [allocating parameters on registers, stack & memory] makes provision for languages other than C and C++ in that it provides for passing arrays by value and for passing arguments of dynamic size.  The rules are defined in a way that allows the caller to be always able to statically determine the amount of stack space that must be allocated for arguments that are not passed in registers, even if the function is variadic.
 

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 6442
  • Country: fi
    • My home page and email address
Re: Memory model for Microcontrollers
« Reply #122 on: May 07, 2024, 10:01:04 am »
:-+

Those wondering, ARM AAPCS = Procedure Call Standard for the Arm Architecture, maintained currently at Github at ARM-software/abi-aa/.

Anticipating the followup question (of how much embedded developers can affect the ABI used): While we can choose from different ABIs, to implement a new one, one needs to add the ABI support to a suitable compiler.  No C or C++ compiler I know of lets an end user define the ABI, although GCC and Clang do let you reserve (a callee-saved) register using -ffixed-register compiler option or as a global register variable.

(On e.g. AVRs, which have 32 8-bit registers, reserving one or two registers (R2 to R17 are callee-saved) allows one to write simple super-lightweight interrupt routines in assembly that use no stack other than their return address, since they can use the reserved register(s) directly.  Say, for example, toggling only a fixed I/O pin will only take about a dozen cycles or so, most of it (~10 cycles) being the typical interrupt overhead on AVR.  For details on the ABI GCC and Clang use on AVR, see avr-gcc wiki.)
« Last Edit: May 07, 2024, 10:12:29 am by Nominal Animal »
 

Offline westfw

  • Super Contributor
  • ***
  • Posts: 4225
  • Country: us
Re: Memory model for Microcontrollers
« Reply #123 on: May 08, 2024, 08:31:40 am »
Quote
using those additional sections
I didn't notice whether it has already been mentioned that between the Gnu linker and "objcopy", there are extensive tools for manipulating sections.  (well, I guess the linker via linker scripts has been well-discussed, but there are other ways as well.)  Objcopy lets you do things like "take this text file and turn it into a linkable data element in the named section"...

For microcontrollers, you need to be a bit careful when converting the .elf file to uploadable formats that all of the relevant sections that you've defined actually make it to the chip.
Quote
[Arduino] was heavily limited by the choice of the GNU g++ compiler, which cannot handle the separate address spaces and machine instructions used to access Flash and RAM, for technical reasons.
My understanding is that C++ standards folk refused to allow the "named address spaces" that were added to C (in gcc versions somewhat newer than originally used in Arduino) and would have permitted transparent access to flash.  Not true?
The newer AVRs have a portion of their flash always mapped into the same 64K address spaces as RAM.  This works fine ("const" data goes into flash) on chips with 48k of flash or less; I don't know about the bigger chips (only 32k at a time is mappable.)



 
The following users thanked this post: MK14

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 6442
  • Country: fi
    • My home page and email address
Re: Memory model for Microcontrollers
« Reply #124 on: May 08, 2024, 11:52:23 am »
Objcopy lets you do things like "take this text file and turn it into a linkable data element in the named section"...
Yes, via
    objcopy -I binary --add-section sectionname=data.bin target.o
Conversely,
    objcopy -O binary -j sectionname source.o data.bin
extracts the contents of a section to a binary file.

The limitation is that this excludes relocation information.  For example, if the data contains addresses of functions or variables, those are lost.  Fortunately,
    objdump -tr source.o
provides enough information to recover those on most architectures.  (To generate C source that recreates the replacement data as an ELF object file.  For example, to sort all entries.)

Moreover, the ELF object file format itself is straightforward to parse.  There are only four variants: 32-bit little-endian, 32-bit big-endian, 64-bit little-endian, and 64-bit big-endian.  I've found it easy to read from e.g. Python (using the struct module), but if one is careful, I've found parsing objdump output quite acceptable, too.  (One just has to ensure that unexpected input is complained about, and not try to parse "almost correct" inputs.)
One useful thing is to also use readelf, because the two (objdump and readelf) are tools intended for roughly the same purpose, but use completely separate source code bases.

Quote
[Arduino] was heavily limited by the choice of the GNU g++ compiler, which cannot handle the separate address spaces and machine instructions used to access Flash and RAM, for technical reasons.
My understanding is that C++ standards folk refused to allow the "named address spaces" that were added to C (in gcc versions somewhat newer than originally used in Arduino) and would have permitted transparent access to flash.  Not true?
The C++ standards folks rejected named address spaces, yes; but like Clang/LLVM, GNU g++ could have implemented them as an extension to C++.

I tried to locate the original discussion a decade to two ago, when named address spaces were initially added to GCC, but could only find bug 69549 which isn't the first time it came up.  The argument was that the g++ developers could not find/decide a workable way the named address space qualifiers would have worked with templates and overloads.  AIUI, Clang/LLVM treats address spaces as a first-level qualifier, i.e. different address-space qualified types are different types, and differ also from the base type.  This seems to work just fine (after initial teething issues!), but the GNU g++ developers do not seem to agree.

Funnily enough, this does affect even x86-64/AMD64, because of FS and GS segment register support; essentially, it has support for three separate address spaces.  The FS segment is commonly used for thread-local storage –– each thread in a process seeing a different chunk of memory there.  (The main tirck is that at offset 0 in that segment is the address at which the segment starts in the normal address space, so that when you apply e.g. address-of operator to a thread-local variable, the compiler doesn't just generate the FS segment address, it takes the TLS segment base address and adds the offset to the variable, generating the address in the global address space.  Darn nifty if you ask me!)  There are shenanigans that could be done with the GS segment register in C++, if GNU g++ would just support named address spaces like Clang/LLVM does.

The newer AVRs have a portion of their flash always mapped into the same 64K address spaces as RAM.
Yes; in general, this is called an unified address space in documentation.
« Last Edit: May 08, 2024, 12:49:22 pm by Nominal Animal »
 
The following users thanked this post: tellurium


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf