Micro Controller, FPGA or ??, I need USB HS and alot of analog

[thewyliestcoyote]

I am working on a project that needs some analog bandwidth. It is a RF transceiver so everything is IQ sampling. What I would like to find is something with at least 2 5MSps ADC and 2 matching DAC's and high speed USB. More bandwidth is better, but that is about all I need. Cost is a big factor so I am not sure there are many FPGA's that make it as none have build in ADC's and DAC's and there does not seem to be any cheap ADC's and DAC's. FPGA would also require the use a ULPI chip.

I have looked at the ST micro's and can't seem to find anything
STM32F3:
    pros:
         2 5 MSps ADC's
         2 4.5 MSps DAC's
    cons:
         Only USB FS

STM32F4:
    pros:
         2 10 MSps DAC's
         USB HS host and device
    cons:
         2 2.4 MSps ADC's(This is 12 bit mode, it 8 bit mode it is closer to 3.2 MSps)

Atmel does not seem to have any micro's with 2 high speed DAC's.

Freescale seems to have DAC's limited to mostly audio type stuff.

I know Lattice and some of the other FPGA vendors have some low cost devices but I think the cost of an external ADC and DAC is to high.

By chance does any one know of a single device that can meet my specs or a low cost ADC and or DAC that can?

Thanks,
Wylie

[mikeselectricstuff]

DACs are pretty rare on MCUs - if you give up looking for that onboard,  that may give you more options.
FPGA cost will be very much down to what you need to do - costs can be from $1 to $1000!
For USB HS, something like an external FTDI FTx232H may be an option.
 
Microchip's PIC32MZ may be worth a look - quick glance at headline specs shows 28MSPS ADC, DSP instructions, HS USB and a buttload of RAM
But check errata carefully - early devices had lots of issues.

[thewyliestcoyote]

I have seen the PIC32MZ's. Cost and board space are at a premium so I would like a onboard DAC. That said I agree 100% the DAC and ADC should not be onboard. Noise and quality are much better.

I should have described the project up front. I am trying to create a cheap half duplex SDR with up to 80MHz-6GHz and +4MHz of analog bandwidth for a student lab. I am trying to keep it under $75 a unit. Also the size should be about that of a large USB flash drive. This is why I am trying to get all the USB and baseband stuff onto one chip.

[BlueBill]

Why not just buy a FunCube? The cost of a from scratch solution would be more.

[thewyliestcoyote]

Transmitter, frequency range, bandwidth, and so on. I need the frequency range and bandwidth for things like channel effects and multipath. Transmission so a student could implement their own protocol.

What I really need is a RTL-SDR that can transmit, bandwidth of 4 MHz, and a frequency range of 80MHz to 6GHz.

[Rasz]

Why not just buy a FunCube? The cost of a from scratch solution would be more.

funcube is $200 .....

cheapest SDR with tx is, or rather will be if it ships, HackRF Blue at ~$200

check out LPC4370 if you want great ADC (80mhz 12bit), airspy sdr uses it successfully
has everything but the DACs
http://www.lpcware.com/content/project/application-example-using-lpc4370-and-labtool-hardware
super cheap devboard 15 euro, full demo board with analog frontend 100 euro
http://www.lpcware.com/lpclink2
http://www.embeddedartists.com/products/lpcxpresso/lpclink2.php

this arm will let you get rid of cpld and adc/dac combo from hackrf, probably ~$20 lower bom right there

[thewyliestcoyote]

I have the LPC4370 board. It is a bit over kill. That said it would be nice to have a IF at 20MHz and digitally down convert it. This was there is no LO leakage into the signal.  Also the LPC4370 only has one ADC so there is going to be some skew or imbalance in I and Q. The HackRF design is a little more then that is needed here. I am doing a lot of tricks to save cost on the RF sections. Also the HackRF has a bit of a problem as some of the maximum parts seem to be coming up on the end of life(#ThanksMaximIntegrated).

[codeboy2k]

<rant>
Grrr... USB terminology... I still can't get my head to remember which is faster, HS, FS, LS, SS

(LS) Low Speed (USB 1.1, USB 2.0) rate of 1.5 Mbit/s (187 kB/s) joysticks.
(FS) Full Speed (USB 1.1, USB 2.0) rate of 12 Mbit/s (1.5 MB/s)
(HS) Hi-Speed (USB 2.0) rate of 480 Mbit/s (60 MB/s).
(SS) Super-Speed (USB 3.0) rate of 4.8 Gbit/s (600 MB/s).

What happens at 10Gb/s ? Ultra-Speed? what about 20 Gb/s.

The 90's and nought's tripped me up all the time with SCSI, FAST-SCSI, WIDE-SCSI, ULTRAWIDE, FASTWIDE, ULTRA160, ULTRA320, grrrr...
I started to get the ULTRA speeds once they started adding bit rates.

USB should just be USB-<speed>

USB-1.5, USB-12, USB-480, USB-4800, USB-10k, etc..

Enough with the marketing names.

</rant>

[thewyliestcoyote]

ERROR missing closing tag of type "speed"! lol

I am not sure when they are going to move off of just using on-off type keying. They are hitting the limit for frequency dispersion of the materials in the cables to make some sort on-off keying reasonable to equalize.

I think Transcend has a trademark on USB ultra speed so that maybe interesting to see how that one plays out.

@BlueBill
I really do like the idea of the funcube. One of the big headaches I am sure to have is USB drivers. The funcube solved that problem is a very awesome way of just using USB audio device protocol. That will not get me up to 4MHz of bandwidth in any reasonable way.

[rx8pilot]

This one should be able to help. May need to tweak the budget somewhat. Still need outboard ADC/DAC's I think.

http://www.digikey.com/product-detail/en/XC7V2000T-G2FLG1925E/XC7V2000T-G2FLG1925E-ND/3981901

[thewyliestcoyote]

HAHA I LOVE IT!!! one chip is more than my years income as a student. And even better yet it is Xilinx so you know the tools are more expensive than the parts. I bet I could do DDS of 6GHz bandwidth of spectrum with that and good ADC's and DAC's. Order better yet just toggle the IO so fast it generates all 6GHz of spectrum at the same time. I think that one chip is about 10 times the project budget for all materials.

[hans]

You may want to double check the STM32 datasheets. According to what I can find, the STM32F407/429 DAC is only an 1MS/s maximum DAC for small changes and a typ. 3us settling time for 10-bit codes +/- 4LSB of end value.

PIC32MZ are plagued by errata, and especially the ADC was a bummer. Initially they announced a 28MSPS ADC, but now dropped it down to basically PIC32MX specs - 10-bit 500ksps.

[andersm]

PIC32MZ are plagued by errata, and especially the ADC was a bummer. Initially they announced a 28MSPS ADC, but now dropped it down to basically PIC32MX specs - 10-bit 500ksps.

The resolution has been downgraded to 8 bits in the latest errata sheets.

[Rasz]

Also the LPC4370 only has one ADC so there is going to be some skew or imbalance in I and Q.

everything has one adc with multiplexers, besides Airspy manages just fine

what was the name of that other cheap sdr with tx? the one using cable modem frontend - that could be a good strategy for you, whole frontend in one chip, makes it 3 chip design (frontend, dac and LPC4370)

[thewyliestcoyote]

Really? damn that is kind of a deal killer for a lot of applications. I wounder what happened. That is a big difference between initial claims and what it can do.

You may want to double check the STM32 datasheets. According to what I can find, the STM32F407/429 DAC is only an 1MS/s maximum DAC for small changes and a typ. 3us settling time for 10-bit codes +/- 4LSB of end value.

They have a app net on getting more out of the DAC's. AN4566 Extending the DAC performance of STM32 micro controllers. See page 7 table 2 indicates 10.5 MSps for the DAC. This difference in performance is from the high output impedance of the DAC and the expectation of some capacitance loading on the output. This can be over come by the use of a external buffer or amplifier in the form of a op amp.

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00129215.pdf

what was the name of that other cheap sdr with tx? the one using cable modem frontend - that could be a good strategy for you, whole frontend in one chip, makes it 3 chip design (frontend, dac and LPC4370)

I have never heard of this is. Can you provide some information more about it? or where to find out more?

[Rasz]

Really? damn that is kind of a deal killer for a lot of applications. I wounder what happened. That is a big difference between initial claims and what it can do.

sample and hold, its not like it samples them in turns

what was the name of that other cheap sdr with tx? the one using cable modem frontend - that could be a good strategy for you, whole frontend in one chip, makes it 3 chip design (frontend, dac and LPC4370)

I have never heard of this is. Can you provide some information more about it? or where to find out more?

3g, not cable modem 
bladeRF and LMS6002D

doable as a DIY project for students in a class:
$25 frontend
$10 LPC4370
leaves you $35 for dac and pcb

osh park 4 layer 150 inches2 = $300, lets make is a 12inch2 boards = $25 per pcb. (No idea if you need 4 layer in the first place)
now to find a $10 DAC and you are set

[thewyliestcoyote]

doable as a DIY project for students in a class:
$25 frontend
$10 LPC4370
leaves you $35 for dac and pcb

While i like the idea of students having to build something, I am not sure It would fly in this case. You know how schools are about building stuff.

osh park 4 layer 150 inches2 = $300, lets make is a 12inch2 boards = $25 per pcb. (No idea if you need 4 layer in the first place)
now to find a $10 DAC and you are set

I is likely to become a 6 layer board and something better than FR4 or FR408. That last part is still maybe but likely. To get 50 ohms on a trace from OSH park is a large trace and for a 4 layer layer it is a small trace. The distance from the outer layer to first inner is 6.7 mils.

$10 for a DAC is on the higher side of the physable cost for a part.

[tggzzz]

Look at the Red Pitaya. TL;DR version is that it is a programmable 100MS/s oscilloscope and analogue controller, based on FPGA and dual-core ARM A9s

[hans]

They have a app net on getting more out of the DAC's. AN4566 Extending the DAC performance of STM32 micro controllers. See page 7 table 2 indicates 10.5 MSps for the DAC. This difference in performance is from the high output impedance of the DAC and the expectation of some capacitance loading on the output. This can be over come by the use of a external buffer or amplifier in the form of a op amp.

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00129215.pdf

I see, they basically try to keep the load impedance down for faster edges.

May want to point at the note that dropped down onto the next page, in which the 10.5MSPS is reached with an "empty" AHB bus. May be wise to just put the ADC and DAC to work via DMA on a STM32F4 discovery board if you decide to go this route, and see how it performs + if there is any jitter/latency issues.

From memory I've had some issues with DMA on the STM32F4, where the delay of a ext. timer trigger to actual SPI clock toggling at 17-odd MHz was in the order of hundreds of nano-seconds.

[thewyliestcoyote]

Look at the Red Pitaya. TL;DR version is that it is a programmable 100MS/s oscilloscope and analogue controller, based on FPGA and dual-core ARM A9s

I dont think that is what I want. It looks like a great scope but going back to what I need it to do and cost. It will not function as a transmitter in much of any of the frequency ranges that I need. Cost at $460 is way too much for this application.

They have a app net on getting more out of the DAC's. AN4566 Extending the DAC performance of STM32 micro controllers. See page 7 table 2 indicates 10.5 MSps for the DAC. This difference in performance is from the high output impedance of the DAC and the expectation of some capacitance loading on the output. This can be overcome by the use of a external buffer or amplifier in the form of a op amp.

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00129215.pdf

I see, they basically try to keep the load impedance down for faster edges.

May want to point at the note that dropped down onto the next page, in which the 10.5MSPS is reached with an "empty" AHB bus. May be wise to just put the ADC and DAC to work via DMA on a STM32F4 discovery board if you decide to go this route, and see how it performs + if there is any jitter/latency issues.

From memory I've had some issues with DMA on the STM32F4, where the delay of a ext. timer trigger to actual SPI clock toggling at 17-odd MHz was in the order of hundreds of nano-seconds.

Yeah I don't think there is any other way of doing this other than using the DMA's for the ADC's and DAC's. There maybe some very very small DSP done on the device(Things like burst tagging for GNURadio). I dont need 10.5 MSps for each DAC, I just need about 4 to 5 MSps for each DAC. Also I am not running the ADC's at the same time as this device is just half duplex.

As for the jitter there is not much else the device is doing so I don't think this will be much of a problem. I maybe able to even run the DAC's and ADC off of the CPU in place of using the DMA. This would leave the USB being the only DMA. Jitter of hundreds of nano-seconds could be a deal killer. I have a couple of STM32F3 and STM32F4 demo boards on order and I will investigate.

[Howardlong]

doable as a DIY project for students in a class:
$25 frontend
$10 LPC4370
leaves you $35 for dac and pcb

osh park 4 layer 150 inches2 = $300, lets make is a 12inch2 boards = $25 per pcb. (No idea if you need 4 layer in the first place)
now to find a $10 DAC and you are set

Good luck making a board with an LPC4370 fanout that OSHPark can fab. You will need to go down to max 5 mil track and gap, and 12mil drill, and be creative. Been there.

The PIC32MZ is one of the biggest disappointments in my electronics career, I unwisely put a product on hold based on the promising PIC32MZ's ADC spec. When I finally got silicon, several months late, I just couldn't get the ADC  to perform. The support from Microchip was deafening by its silence, in the UK their sales people knew nothing about the devices, and they weren't interested in helping me despite having a reasonable record of buying tens of thousands of PIC24 and PIC32s with them. In the end I threw in the towel, but I lost about nine months' development time as a result, and went with the LPC4370, which has been a very steep learning curve, but it works. You can get around the single s/h with either (a) your own s/h [reasonably hard at this sample rate!], (b) all pass filter, or (c) in host software with, say, a fast convolution.

[thewyliestcoyote]

doable as a DIY project for students in a class:
$25 frontend
$10 LPC4370
leaves you $35 for dac and pcb

osh park 4 layer 150 inches2 = $300, lets make is a 12inch2 boards = $25 per pcb. (No idea if you need 4 layer in the first place)
now to find a $10 DAC and you are set

ood luck making a board with an LPC4370 fanout that OSHPark can fab. You will need to go down to max 5 mil track and gap, and 12mil drill, and be creative. Been there.

I had not planned on using OSH park for any finished devices and not because I don't like the service. Their specs just don't work for microwave circuits. The 6.7 mil layer of pregrag is way too thin to make microwave filters and other distributed element filters effectively and FR4 and FR408 is just to lossy.

One proposed topology is to transvert everything from the low frequency to the high frequency stuff up to X band or higher then mix it back down. This is because of the cost and size of components at 6GHz frequency range. distributed element circuits are cheaper, lower loss, and at higher frequency smaller. It is much cheaper to get high quality LO's at these frequency than lower frequency.

Given the desired size of the radio I am stuck using BGA's in the complete device.

The PIC32MZ is one of the biggest disappointments in my electronics career, I unwisely put a product on hold based on the promising PIC32MZ's ADC spec. When I finally got silicon, several months late, I just couldn't get the ADC  to perform. The support from Microchip was deafening by its silence, in the UK their sales people knew nothing about the devices, and they weren't interested in helping me despite having a reasonable record of buying tens of thousands of PIC24 and PIC32s with them. In the end I threw in the towel, but I lost about nine months' development time as a result, and went with the LPC4370, which has been a very steep learning curve, but it works. You can get around the single s/h with either (a) your own s/h [reasonably hard at this sample rate!], (b) all pass filter, or (c) in host software with, say, a fast convolution.

Yeah that is kind of a big deal the difference in performance gap. How did that happen, someone in marketing order a engineer from another product line or something? that makes no sense.

I know ARM M4's are very very good at doing filtering, maybe one of the better architectures in this range. That said I agree about the learning curve as to get the most you either pay a arm and and a leg for libraries and compilers or write what you need to be fast in assembly. I still am amazed that none of the vendors have added support for things like a FIR optimized pipeline that does not require the CPU.

 I am cheap and going to try and make this project open source so assembly for me it looks like.

Someone PLEASE FIND ME A CHIP FPGA OR CHIP with ADC's, DAC's, and USB so I don't have to program in assembly. I have payed my dues already to the assembly god's and thought I was done.

[nctnico]

AFAIK NXP or ARM offer extensive DSP libraries so no need for assembly programming.

[tggzzz]

Someone PLEASE FIND ME A CHIP FPGA OR CHIP with ADC's, DAC's, and USB so I don't have to program in assembly. I have payed my dues already to the assembly god's and thought I was done.

Firstly I don't see what the level of silicon integration has to do with your choice of programming language.

Secondly, you do realise that there would be a lot of digital noise coupled into the analogue circuits. It is difficult enough to sort that out at the board level, and much more difficult inside a single chip.

Finally, you do realise that, for high performance analogue, the analogue and digital transistors are based on very different processes.

(And the Red Pitaya has significant analogue outputs; some people are using it as a sig gen + scope => network analyser.)

[thewyliestcoyote]

AFAIK NXP or ARM offer extensive DSP libraries so no need for assembly programming.

Good to here!

Firstly I don't see what the level of silicon integration has to do with your choice of programming language.

You are right very much right but. If there is no support for optimized DSP and other optimized functions these would almost certainly require some hand optimizations ie assembly. I know I am not the most articulate person and here it has shown thou here.

Secondly, you do realise that there would be a lot of digital noise coupled into the analogue circuits. It is difficult enough to sort that out at the board level, and much more difficult inside a single chip.

Finally, you do realise that, for high performance analogue, the analogue and digital transistors are based on very different processes.

Yes I very much do, It comes but to what I am trying to. I am not making the next greatest spectrum analyzer, VSA, VSG, or VNA. I am trying to make a cost effective tool for student labs. This way the students can buy there own hardware and do the labs at home or ... . This is why I am trying to keep the cost down to the very very minimum while still having some performance*. If there was a RTL-SDR that was also a transmitter and could extend into the 6GHz range. This way students could have some hands on expense with channels that are more then 1 or 2 lambda and have a lot of multi-path.

I am a little confused why you are recommending the Red Pitaya. Seem like a great product and I have been interested in getting my hands on one for some time now for personal use. It does not any of the things that I need for undergraduate and graduate communications classes. It seems to have a -3dB point of just 50MHz. This is more then enough for a lot of applications but not this one. Also it fails to meet the price spec. Students can not by 2 $450 devices. That is like the price of one new text book nowadays  .

(And the Red Pitaya has significant analogue outputs; some people are using it as a sig gen + scope => network analyser.)

When you need a VNA you need a VNA and most likely a lot of performance from it. This is why I have a few of these at work and not just a couple of scopes and signal generators.
http://www.keysight.com/en/pd-1654293-pn-N5245A/pna-x-microwave-network-analyzer?
Its all about hte right tool for the job.

[andersm]

Yeah that is kind of a big deal the difference in performance gap. How did that happen, someone in marketing order a engineer from another product line or something? that makes no sense.

It's probably no coincidence that the PIC32MZ was pushed through the door unfinished, and untested, just before the end of the year. My personal guess is that Microchip had some contractual obligations to meet, because I can't see anyone being happy with the device in its current state.

[thewyliestcoyote]

It's probably no coincidence that the PIC32MZ was pushed through the door unfinished, and untested, just before the end of the year. My personal guess is that Microchip had some contractual obligations to meet, because I can't see anyone being happy with the device in its current state.

Not to long after the PIC32MX first came out I got my hands on a couple. I bricked all of them with silicon bugs that microchip had not fixed(Something with programming with the pikit3 and the PIC32's did not like each other). Guess it is not the first time Microchip has pushed something out the door before it was ready. If all someone wanted was a RAM and flash upgrade of the PIC32MX then I am sure they are happy. I still cant get over that whole ADC thing. Something is just not adding up to be a order of magnitude off. I mean what happened? how does a company say that they will have a product that can meet some spec and be that far off? They not do there homework? not know how to design a ADC?

Either way still does not have a on-board DAC or have not found a cheap external DAC so does not effect me.

[tggzzz]

If there was a RTL-SDR that was also a transmitter and could extend into the 6GHz range. This way students could have some hands on expense with channels that are more then 1 or 2 lambda and have a lot of multi-path.

I am a little confused why you are recommending the Red Pitaya. Seem like a great product and I have been interested in getting my hands on one for some time now for personal use. It does not any of the things that I need for undergraduate and graduate communications classes. It seems to have a -3dB point of just 50MHz.

I'm not recommending the Red Pitaya. It appeared you had rejected it (OK no problem with that) based on misunderstanding what it could do (which might have been a shame).

Good luck getting 6GHz bandwidth ADCs DACs and processors at a reasonable cost! I haven't seen what bandwidth you want, but most people would up/down-convert a baseband signal to 6GHz or whatever.

Certainly 50MHz is sufficient to see multipath in cellphone systems, and for a rake receiver to extract the next 3dB.

[thewyliestcoyote]

Good luck getting 6GHz bandwidth ADCs DACs and processors at a reasonable cost! I haven't seen what bandwidth you want, but most people would up/down-convert a baseband signal to 6GHz or whatever.

Certainly 50MHz is sufficient to see multipath in cellphone systems, and for a rake receiver to extract the next 3dB.

There is almost certainly a bit of confusion here on both our parts. I have only rejected it for my current assignment. Cost is the factor that is making this possible. As much as I would like to say I am done and move on to the next project. $450 each with with frequency range of 0 to 50MHz is a failure of about 10 times the end cost and missing much needed function. I do work for the government but for a university not the defense system where cost over runs seem to be encouraged  .

There is no transverter build into the Red Pitaya so it can not be used for frequencies of greater then 50 MHz or so. I am not sure of the input topology so it may have some aliasing problems. (when pushed most things seem to, High end scopes and spectrum analyzer included. ) This is would not be a problem it as 50 MHz of bandwidth is well beyond what I need here.

But going back to the original goals of the project I only need 1 Rx and 1 Tx channel, 4 MHz of analog bandwidth equivalent for capture, and a frequency range of about 80MHz to 6GHz. Looking at the Red Pitaya it uses linear tech ADC LTC2145CUP-14 and a  DAC1401D125HL. The ADC has a unit cost of $60 for 100 of qty. The DAC seems a bit better at $11 in qty of 250. Still a bit on the high side but maybe possibility. It does seem to be a bit over kill at 125MSps. maybe something half or 1/3 the cost with 1/10 the sample rate would be just fine.

[Rasz]

But going back to the original goals of the project I only need 1 Rx and 1 Tx channel, 4 MHz of analog bandwidth equivalent for capture, and a frequency range of about 80MHz to 6GHz.

another ghetto idea - how about designing only the TX part? you can leave rx to a pair of RTLSDRs. You can sync couple of dongles by using same clock source.

[Howardlong]

Good luck getting 6GHz bandwidth ADCs DACs and processors at a reasonable cost! I haven't seen what bandwidth you want, but most people would up/down-convert a baseband signal to 6GHz or whatever.

Agreed. The OP may not be aware, but I have been involved commercially in this space with products of my own design for several years.

The standard method for much over a few tens or hundreds of MHz is to downconvert in the analogue domain either to ZF or low IF, ADC, and digital downconvert if not already at baseband. You can use harmonic sampling too, but you'll need and ADC with sufficient bandwidth, plus some nice bandpass filtering in the analogue domain. If you're trying to subsample a 6MHz bandwidth signal on a 6GHz carrier, that's going to need quite some filter, and if you want frequency agility too, you'll need a lot of them!

Similarly for transmit, unless you're transmitting constant envelope, a similar method is used in reverse.

So just for the analogue down conversion for the receiver and up conversion for the transmitter you need to find a wideband LO, and a very wideband quadrature modulator and demodulator. There are a very few devices at do this in a single integrated package.

In addition for transmit, you may want to consider if half duplex is reasonable depending on your image and LO leakage mitigation if required. Being able to operate full duplex means you can also correct DC offset and IQ imbalance in your transmitter.

Basically, if you think you can make your design for peanuts, you are going to have to try very hard. If you do a BOM and assembly cost for those RTL dongles, it's not actually possible to make them for the price they're sold at retail unless you are making hundreds of thousands of them.

[thewyliestcoyote]

But going back to the original goals of the project I only need 1 Rx and 1 Tx channel, 4 MHz of analog bandwidth equivalent for capture, and a frequency range of about 80MHz to 6GHz.

another ghetto idea - how about designing only the TX part? you can leave rx to a pair of RTLSDRs. You can sync couple of dongles by using same clock source.

Oddly enough for another project I have tried something like this. I had 9 of them linked to gather to do angle of arrival estimation. Short answer is this was kind of point less at it is not possible to get phase lock form those devices. Fun project tho.

The standard method for much over a few tens or hundreds of MHz is to downconvert in the analogue domain either to ZF or low IF, ADC, and digital downconvert if not already at baseband. You can use harmonic sampling too, but you'll need and ADC with sufficient bandwidth, plus some nice bandpass filtering in the analogue domain. If you're trying to subsample a 6MHz bandwidth signal on a 6GHz carrier, that's going to need quite some filter, and if you want frequency agility too, you'll need a lot of them!

I am currently looking at a 2 stage conversion to baseband. I have kind of a high some where from 900MHz to 1600MHz IF but that is because of some other components and design choices. I have no plans of doing a zero IF design or anything like that. That is just not what is needed here or reasonable. The IF is very narrow relative bandwidth thanks to cheap saw filters. For the base band I have designed a couple elliptic filters that meet all the specs that I need. For the front end there is 3 or 5 band pass filters in parallel selected by a switch network. Nothing is final yet so all subject to change.

In addition for transmit, you may want to consider if half duplex is reasonable depending on your image and LO leakage mitigation if required. Being able to operate full duplex means you can also correct DC offset and IQ imbalance in your transmitter.

This is half duplex. I cant think of a reason that needs full duplex here. Always nice to have more features but I am not sure that full duplex has a place here. Maybe some one will persuade me and I will be forced to add it in.

[Rasz]

But going back to the original goals of the project I only need 1 Rx and 1 Tx channel, 4 MHz of analog bandwidth equivalent for capture, and a frequency range of about 80MHz to 6GHz.

another ghetto idea - how about designing only the TX part? you can leave rx to a pair of RTLSDRs. You can sync couple of dongles by using same clock source.

Oddly enough for another project I have tried something like this. I had 9 of them linked to gather to do angle of arrival estimation. Short answer is this was kind of point less at it is not possible to get phase lock form those devices. Fun project tho.

did you feed all of them from the same clock source? people tried with success and little phase noise
http://gnuradio.4.n7.nabble.com/dual-coherent-channel-rtl-sdr-td43784.html
http://kaira.sgo.fi/2013/09/16-dual-channel-coherent-digital.html
+need tuned 820 pll code (disabled dithering).

[Howardlong]

The reason for full duplex is that that I offered, i.e. a way to correct for IQ imbalance and/or LO leakage in the exciter by analysing your own signal in real time. If you're not interested in that, or it's unnecessary in your design then that's fine, I was just offering a suggestion to you. It's just that it's quite common to do exactly that in single conversion quadrature upconverters by analysing the output in real time and correcting for it by tweaking the baseband. If you're not doing that, then that's fine, I was just trying to offer you some help and suggestions!

[thewyliestcoyote]

did you feed all of them from the same clock source? people tried with success and little phase noise
http://gnuradio.4.n7.nabble.com/dual-coherent-channel-rtl-sdr-td43784.html
http://kaira.sgo.fi/2013/09/16-dual-channel-coherent-digital.html
+need tuned 820 pll code (disabled dithering).

Glad to hear that some one got it to work. I wish I had seen that when I was trying that. I am still not sure that it would have worked for what I was doing. I found that out after a lot of time with the chip set documentation. It is designed for frequency lock, not phase lock between 2 or more of them. What I needed was phase lock because of doing angle of arrival form time of arrival. I am sure that I could calculate the phase offset in real time, but that was more then I wanted to do. Solution by a better set of radios. BTW for the clock source I was using a couple different things, mainly a signal generator with a very nice 10MHz reference.

The reason for full duplex is that that I offered, i.e. a way to correct for IQ imbalance and/or LO leakage in the exciter by analysing your own signal in real time. If you're not interested in that, or it's unnecessary in your design then that's fine, I was just offering a suggestion to you. It's just that it's quite common to do exactly that in single conversion quadrature upconverters by analysing the output in real time and correcting for it by tweaking the baseband. If you're not doing that, then that's fine, I was just trying to offer you some help and suggestions!

Hmm, had not though about that for the use for this. The DAC's and ADC's have a common baseband (cost savings).

Maybe something I can do it in the baseband to adjust the balance. I will give it some thought. I don't really have the hard on the board to have it transmitting and receiving at the same time. This is not the highest preforming device tho like I said. As much as I would be the one that builds the next best VNA, VSG, and VSA all in one but this is not the project for it. I am trying to get something like ~35dB of range of the captured signal. A lot of the mixers that I am looking at have LO rejection of better then 40dB when used correctly. Total dynamic goal has not been selected yet.

And many thanks for the suggestions.
I am always welcome to hear them, even if I sometimes sound like a ass-hole sometimes.
I am not trying to be one.