STM32 PLL clock source doesn't work

[mikewax]

hello i wonder if any STM engineers can see what's wrong with my code. it's an STM32F030F4P6 chip. all it does is blink an LED. the problem is i set the system clock as HSI/2 * PLL multiplier. so it's supposed to be 8MHz/2 * 12 = 48MHz. so the macro RCC_CFGR_PLLMUL12 determines the PLL multiplier. but when i change the 12 to a 2 as in RCC_CFGR_PLLMUL2 the LED frequency does not change. the system clock frequency is the same with 2 as it is with 12.

Code: [Select]

#include "stm32f030x4.h"

int main(void)
{
 // sysclock configuration
  RCC->CR |= RCC_CR_HSION;
  RCC->CR |= RCC_CR_PLLON;
  RCC->CFGR &= ~RCC_CFGR_PLLSRC;
  RCC->CFGR |= RCC_CFGR_PLLSRC_HSI_DIV2;
  RCC->CFGR &= ~RCC_CFGR_PLLMUL;
  RCC->CFGR |= RCC_CFGR_PLLMUL12; //   <----- changing the multiplier has no effect
  RCC->CFGR &= ~RCC_CFGR_SW;
  RCC->CFGR |= RCC_CFGR_SW_PLL; // PLL on
  RCC->CFGR &= ~RCC_CFGR_HPRE;
  RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // sysclk (ahb) not divided
  RCC->CFGR &= ~RCC_CFGR_PPRE;
  RCC->CFGR &= RCC_CFGR_PPRE_DIV1; // apbclk not divided
  RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
 
 // GPIO pin configuration
  pinpos = 4;
  GPIOA->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (pinpos * 2));
  GPIOA->OSPEEDR |= ((uint32_t)(0x03) << (pinpos * 2)); // high speed 50MHz
  GPIOA->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
  GPIOA->OTYPER |= (uint16_t)(((uint16_t)0x00) << ((uint16_t)pinpos)); // type push/pull
  GPIOA->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
  GPIOA->MODER |= (((uint32_t)0x01) << (pinpos * 2)); // mode = output
  GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
  GPIOA->PUPDR |= (((uint32_t)0x00) << (pinpos * 2)); // no pull

    while(1){
    GPIOA->ODR ^= (1 << 4);     // toggle LED
    for (y = 0; y<500; y++){        // delay about 1 second
      for (x = 0; x<500; x++){}
    }
  }
}


[newbrain]

I did not check in detail, but this looks very suspicious:

Code: [Select]

  RCC->CFGR &= RCC_CFGR_PPRE_DIV1; // apbclk not divided


This line will clear most of the configuration you've previously set up.

Edit:
Some more findings:

• The PLL related bits in RCC_CFGR cannot be changed with PLL on, so RCC->CR |= RCC_CR_PLLON; should be moved after the PLL multiplier configuration: see ch. 7.4.2 in the RM.
• After switching on the PLL, one should wait for the PLLRDY bit to be set to make sure it's locked (though the system clock selection will wait for it automatically).
• The description of how to modify the PLL settings is in ch. 7.2.3 of the RM.
• In this case it should not be harmful (as all the bits you are changing have 0 reset value), but in general it would be better to read the configuration in a temporary variable, set and reset the needed bits and write it back to the configuration register. This avoids changing the configuration twice for a single operation.

[technix]

I think this code example should tell something:

https://github.com/xcvista/STM32F407-Startup/blob/master/platform/src/system_stm32f4xx.c

This code is based on STM32F407, but the general procedure of STM32 clock tree manipulation should be the same.

[newbrain]

Yes, thanks.
The original code does work too, once the &= is addressed and the enable PLL position corrected: checked, on a 072.

Not that the OP would seem to care