Here's the official I2C specifications:
I think you're missing my point. If you have a system in which two devices communicate with each other using "I2C", the chances of that 'official' I2C spec actually applying to either of them are minimal. Much more likely is that one device has a broadly I2C-compatible two wire serial interface, and the other will have a pair of GPIO pins which are driven by software in a way which mimics the approximate behaviour of a 'real' I2C-compliant master.
Neither will actually be 'officially' I2C compliant. If they were, then they'd have to pay patent royalties to NXP.
That usually never happens as I pointed out. Yes, Linear makes an IC for 4 USD, which can replace two 1 cent resistors.
It can and does happen, I've done it myself. If you have a heavily loaded bus, the capacitance makes for a very slow rise time when the lines are released and allowed to be pulled high. Achieving a faster rise time means using a lower resistance (smaller RC time constant), but that means more DC current is drawn when the lines are at logic 0. Depending on the drive capabilities of the devices on the bus, this can mean the logic 0 level ends up too high to be valid.
To work around the problem, the driver can actively drive SCL and SDA high, just for a moment, before releasing the pin and allowing it to be driven low by other devices. This very brief period of active driving is all that's needed to charge the bus capacitance, so the signal rise time can be short and the overall throughput can be increased.
All you need to be aware of is that nothing else should be driving the bus low at the instant the 'active' device drives high - but even then, a few ns of bus contention is unlikely to do any harm. It would only happen if a slave device were trying to do clock stretching - but it's rarely needed, and most "I2C" components don't support this feature anyway.