So please lets stay with the initial system originally described, it's requirements, and focus on the microcontroller, which is where we need some quidance!
What we need the microcontroller to do is create a set of 8 sequential non-overlapping pulses of varying width (0.5 to 5ms), at a rate of ~4Hz to ~80Hz selectable. Another output is a selectable timer from ~60sec to ~1800sec. Everything is ~6 bit resolution, except the analog input at ~8bit resolution.With a pulse train like that, you may be better to define to edge toggle times, and have small slaves you send a pulse-set to, and then trigger.
If that becomes firmly defined, that pulse set can go into code FLASH.
You may be able to scale this, to fit into the common 16 bits timer size
eg if you need 0.5ms to 6 bits, that 10us LSB can define to 0.655 seconds
AVR's have timer prescalers with fairly coarse choices, but that may be 'good enough'.
The 8051 families have a PCA with a HSO mode, which toggles a pin on a match setpoint, and finer prescaler choices.
The SiLabs EFM8BB5x series have 50MHz sysclks, which gives good headroom.
The BB52 has 3 PCA channels, but you can shift them along the pins, so if your pulses never overlap, you can have more pulsing pins.
If you need precision PWM, the STC8H family have 8 x 16b PWM's with a nice fine 16b /N prescaler and TSSOP20/TQFP32 packages
Some 8b MCU's are getting > 100MHz PWMs, but you are not quite pushing that territory.

Maybe get some low cost eval boards, and try creating some example pulse trains.
If I was coding an experimental/flexible pin pulse generator, I might pick a EFM8BB52, and allocate 4 bytes per edge : The lower 2 are HW timer match, 3rd byte is SW timer match, and upper byte is pin select + toggle enable + spares.
Pulses longer than 2^16 would need some packer values, ie time stamps without toggles, as HW simply left alone will toggle once every 2^16.
Software updates times place a rule on shortest possible pulse, something less than maybe 100 sysclks would need care, ~2us tho more HW via CLU logic or external XOR could drop to 1 sysclk.
A RPi or any host could generate and send those pulse records and then trigger the MCU's on a trigger pin.
You did not explicitly state the edge precision and total number of edges, or the total timing precision (on chip OSC or external OSC) ?