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Microcontroller suggestion

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fabiodl:
I would like a microcontroller with the following features:
- it exposes a parallel address/data/control bus, to which I can connect memory mapped devices (like a  motorola 68000)
- it has a wait/ready line which can make it halt during a read write (again, like a motorola 68000)
- its toolchain is open source and well supported
- it is not a softcore (i.e. it is not picorv32 )
- it is relatively fast (just to give an idea, over 1 MIPS)
- it is under 20 bucks
- it is currently sold
- bonus points if the default library supports floating point operations, i.e. it has enough ram /rom to support newlib or it uses avrlib
- bonus points if it's risc-v based

dobsonr741:
RP2040 with the PIO emulating the bus.

SiliconWizard:

--- Quote from: dobsonr741 on June 04, 2023, 04:31:22 am ---RP2040 with the PIO emulating the bus.

--- End quote ---

Yes, the only downside is the limited number of GPIOs. That's quickly going to be a problem for interfacing parallel memory with an address, data and control bus.

Another option would probably be the much beefier and more expensive NXP iMXRT 106x series. Very flexible interfacing, many more GPIOs, much more powerful, and still below the 20 bucks mark.

For other common MCUs, that'll be hard to fit the bill. Many have some kind of memory interface, such as STM32's FSMC, but while it can be configured in various ways with configurable wait states and such, I don't think it's capable of doing the handshaking (the OP's wait/ready line.) This last point will restrict the choice of MCU drastically.

brucehoult:

--- Quote from: fabiodl on June 04, 2023, 04:12:39 am ---I would like a microcontroller with the following features:
- it exposes a parallel address/data/control bus, to which I can connect memory mapped devices (like a  motorola 68000)

--- End quote ---

That is just about the definition of "What is the difference between a microprocessor and a microcontroller".

You can always implement whatever external bus you want using GPIOs if you have enough of them and the bus doesn't have to operate at super high speed.

ATMega2560 supports external RAM (or whatever) in hardware using PG0-2 for control and PA0-7 and PC0-7 for the address. D0-D7 use the same pins as A0-A7 so you need an external latch for the low address bits. External memory adds 1 wait state I believe.


--- Quote ---- it has a wait/ready line which can make it halt during a read write (again, like a motorola 68000)

--- End quote ---

No idea. Of course if you implement everything yourself using GPIOs then you can do whatever you want.


--- Quote ---- its toolchain is open source and well supported
- it is not a softcore (i.e. it is not picorv32 )
- it is relatively fast (just to give an idea, over 1 MIPS)
- it is under 20 bucks
- it is currently sold
- bonus points if the default library supports floating point operations, i.e. it has enough ram /rom to support newlib or it uses avrlib

--- End quote ---

All easy.


--- Quote ---- bonus points if it's risc-v based

--- End quote ---

Harder.

Kendryte K210 has 8 MB of internal RAM and supports 8 MB of hardware-controlled external SPI RAM (which could of course be MMIO if you want).

hans:
Look at F(S)MC of STM32F4, and possibly also present in other families (e.g. F2 F7 H7). In NOR/PSRAM mode it has a NWAIT signal that is an input to the MCU to wait on the memory device. The downside is that the data D[15:0] and address A[25:16] + A[15:0] is partially multiplexed.
These devices can support a reasonably large address space plus a 32-bit data bus.

One thing to test is whether that mode supports reads and writes, and how the asynchronous behaviour then works.
For example, the QuadSPI controller in some STM32 devices could also be memory mapped, but was only intended for reads from FLASH as it only supported a single instruction opcode to initiate random addressing. If it was used in direct mode, it could do both read and writes.

I think many other memory busses will have controllers that communicate in terms of synchronous transactions, and assumes a fixed number of dummy clocks (as latency) before the memory device will reply. That's how a lot of these FLASH and S(D)RAM chips work anyway.

I'm not sure if its an exact for the devices you want to communicate with. I think other options would quickly converge to a FPGA, but I will not challenge the presumption that 'no softcore' also means no FPGA/custom logic fabric solution (be it glue or as a complete controller).

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