I bet it was a DSP then cuz they have a rather unique way about them. DSP56001 or maybe I'm thinking of the intel 8031 family ?
(my first board, designed and handmade in 1994. It was loaded with Intel basic 51)
(the board was designed by following this book, printed by Intel and offered)
Intel 8051 is Harvard in the meaning it uses a special signal "/psen" for acknowledging the code-area, but data and addresses are shared between the code space and the data space.
See the pic, you can see the memory mapped I drawn years and years ago. Note the two spaces are separated even if addresses numerically collide (except for the trick for the three NVRam Chips that are mapped in both Code space and Ram space thanks to the Intel's trick described in the book).
This is clearly not a "structural hazard", it's simply a way to distinguish the data from the code, and there are tricks (reported by Intel in the above book) for being able to read and write into the code space so a bootloader can be written in a way it can reprogram its own flash. Otherwise ... you cannot on-board reprogram an 8051's flash and you end by programming the chip manually with an external tool (e.g. ROM-emulator, or prom programmer).
The DSP56001 is a "modified Harvard architecture" processor with three memory spaces and on-chip memory banks in some of the models. It allows the contents of the instruction memory to be accessed as if it were data and it's a weird beast with the uncommon data size of 24 bit.
A pure RISC-Harvard machine expresses the need to have the code space and the data space in a way the CPU can fetches opcodes and simultaneously accesses the Ram. In this case, the purpose of being "Harvard" is clearly an attempt to solve the "structural hazard" in a way that fetches and IOs can be performed simultaneously.
This is a need for the pipeline and modern pipelined-RISC-ish CPUs and MPUs are all "modified Harvard architectures" or "pure Harvard architectures with *the bridge*"