Microcontrollers with fastest ADCs?

[dmendesf]

I'm makinga list of the microcontrollers with fastest ADCs.
I have:
LPC4370FET256 - 80Msps 12 bit single ADC, but BGA package
MSP430FR6047 - 8Msps 12 bit single ADC, 100tqfp
STM32H7 - triple 4Msps 16 bit ADC, multiple packages
PIC32MK - seven 3.75Msps 12 bit ADC, multiple packages

Am I missing something?

[MasterT]

STM32F303xE - 4 x 5.1 Msps 12-bits, LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 x 20 mm)

[NorthGuy]

PIC32 MZ 6 x 3.125 Msps or up to 12.5 Msps when interleaved (12 bit)

[Rasz]

nothing beats LPC4370. BGA is not a huge problem, you will want at least 4 layers with 80MHz signals flying around anyway.

[MasterT]

I played recently with STM32F3 /F4, and find out that there is a big difference between "up to XXX MHz" and data rate that uCPU could really support.   
Example, STM32F446RE running internal core at 180 MHZ is able to read GPIO 8-bit port at 11.25 MHz max. It seems that readings could get 36 Msps score, but "hardware" check with synchronous counter connected to GPIO shows missing samples.

STM32F303RE though has 4x 5.1 Msps 12-bits ADC, but unable to read   20.4 Msps 12-bits data stream, due to DMA bottle neck limits. 
Max. what I get is 20.4 Msps 8-bits. OR about 16 Msps 12-bits.

 It makes me skeptical if NXP really solved DMA interference issue

[Rasz]

It makes me skeptical if NXP really solved DMA interference issue

works fine, small internal sram and slow USB are the limits to usefulness
https://community.nxp.com/thread/429528#comment-1024021

[MasterT]

It makes me skeptical if NXP really solved DMA interference issue

works fine, small internal sram and slow USB are the limits to usefulness
https://community.nxp.com/thread/429528#comment-1024021

 Have no idea how this technic works:

I can confirm I can reliably sample at 80MHz to internal SRAM memory without loosing any samples, my system samples an ultrasound signal so any lost samples will be evident and cause a problem.

as a verification tool, I can only say, that it's not a rocket science to set secondary timer with RC at any spare GPIO pin to generate synchronous triangle wave,  in order to "visually" confirm presents each and any sample in correct order in the sampling buffer.

 It's make me even more skeptical. I do not like to comment on a content of another forum, and do not have an experience with NXP products,  but Cortex-M4  should not have much difference  between STM and NXP? And since NXP  not invented new dedicated DMA bus to ADC, or reasonably sized FIFO to get all samples at once, I don't see any reason why LPC would ever break DMA barrier.
 There are many people who think the same:  https://community.nxp.com/thread/420407
 laying this barrier at about 25 MHz for 200 MHz core clock. 

[SiliconWizard]

LPC4370FET256 - 80Msps 12 bit single ADC, but BGA package

Wow, impressive beast! It's not even expensive for the specs - around 10 bucks.

You may add the Analog Devices ADSP-CM4xx line to the list. Up to 16-bit ADCs, > 2MSps.

[mac.6]

It's make me even more skeptical. I do not like to comment on a content of another forum, and do not have an experience with NXP products,  but Cortex-M4  should not have much difference  between STM and NXP? And since NXP  not invented new dedicated DMA bus to ADC, or reasonably sized FIFO to get all samples at once, I don't see any reason why LPC would ever break DMA barrier.
 There are many people who think the same:  https://community.nxp.com/thread/420407
 laying this barrier at about 25 MHz for 200 MHz core clock.

DMA has nothing to do with Cortex M core. Most vendors do not use ARM IP for dma, but their own tied to internal buses which dictate DMA max troughput/latencies/priority.
In fact NXP has a dozen different DMA engines between legacy nxp, freescale, quintic, and other mcu lines...

[mark03]

It might be more interesting to compare these taking into account how many of the bits are actually good.  ENOB isn't the be all / end all of ADC specs, but it says more than just the headline resolution in bits.  Basically what you want to know is, which ADC is providing the most information per unit time.  In white noise I guess you could define a figure of merit like "number of effective bits in a 1 Hz bandwidth":

F.O.M. = ENOB + (log2(samplerate) / 2)

or something like that.

[Doctorandus_P]

Many years ago I bumped into a datasheet of an unknown chip.

The description on the front page was:
24 bit adc with integrated microcontroller.
But it was not very fast.

How many bits does it need to have?
If one is enough you can use any digital input pin, some also have an analog comparator as input.

[dmendesf]

Both Analog Devices and Texas have microcontrollers (8051 and cortex-m3 if memory serves well) with 24 bits ADCs, but these are sigma-delta, so very slow. I've been doing some "fast" (1khz - 500khz) signal processing in the last 10 years. Used to need a FPGA + external ADCs to do it. Lately a stm32 started to fill the needs. I was just wondering if I'm missing some interesting device out there.

[Gribo]

The TI Chips are the MSP430AFE2xx. Practically, a 0.25KB ram, 8KB flash, UART and a 24bit ADC in one chip.