In prep. for an upcoming exam on VHDL design, I've been going through previous years exams. There's a sort of bonus/advanced multiple choice section on ASIC design and I'm a little stuck on one of the questions.
The question reads;
In a 0.18 micron process:
A. all transistors are 180nm wide
B. lambda = 90nm
C. the narrowest polysilicon track is 0.09 microns wide
D. all nFETS are 0.18 microns wide.
I've been reading around online but haven't found many resources which explain the process enough to help answer the question.
Anyone know of any material on this that could help?
If were to answer this question now, my answer would be B.