Author Topic: MIPI screens for STM32, quantity of data lanes.  (Read 2184 times)

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Offline luiHSTopic starter

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MIPI screens for STM32, quantity of data lanes.
« on: February 09, 2022, 11:01:58 pm »
Hello.
I have several designs to make, some already advanced, using small screens. I decided to use MIPI interface because they need much less tracks than a parallel interface.

The problem is that I find some screens that interest me because of their size (3.95 inches square), but their MIPI interface is for 4 data lanes, when my hardware can only handle up to 2 data lanes.

On the other hand, NXP evaluation boards are using 4 data lane displays, even though the RT1176 microcontrollers can only handle up to 2 data lanes on their MIPI interface.

The strange thing is, for example, that I find 800*480 resolution screens that are controlled with 2 data lanes, and others of 640*480 or 720*720 that have 4 data lanes. I thought that depending on the resolution of the screen, more or less data lanes are needed.

The question is if it is possible to handle with only 2 data lanes a MIPI screen that has 4 data lanes in its pinout. Perhaps the resolution is lower, something that does not worry me, I could continue using them for my applications.

« Last Edit: February 09, 2022, 11:06:17 pm by luiHS »
 

Offline thm_w

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Re: MIPI screens for STM32, quantity of data lanes.
« Reply #1 on: February 10, 2022, 01:12:13 am »
Quote
On the other hand, NXP evaluation boards are using 4 data lane displays, even though the RT1176 microcontrollers can only handle up to 2 data lanes on their MIPI interface.

Do they provide schematics or code for their eval boards that you can look at?
Maybe they are sacrificing update rate, color depth, or some other aspect.
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Offline luiHSTopic starter

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Re: MIPI screens for STM32, quantity of data lanes.
« Reply #2 on: February 10, 2022, 02:49:12 am »
Yes, NXP and ST provide schematics of their evaluation boards.
https://community.nxp.com/t5/i-MX-RT/LPSPI-in-interrupt-amp-eDMA-mode-not-working-in-RT1170-EVK/m-p/1384447?attachment-id=126920

I read something that in some MIPI screens 4 data lanes can be used with 2 data lanes, that can limit the fps, but still it seems that they must be configured by hardware to define how many data lanes are used, and that is not available in all screens.

I found this document about using 4 data lane displays with STM32H7 microcontrollers.
https://pcbartists.com/design/embedded/using-4-lane-mipi-dsi-display-with-stm32-2-lane-dsi-host/

Now I'm thinking of doing some projects with parallel RGB screens, it will be more complicated to route the PCB, but I won't have this problem.
« Last Edit: February 10, 2022, 02:54:37 am by luiHS »
 
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