My first STM32 design

[Siwastaja]

Rookie question.

I've seen this weird stuff on some datasheet I've been reading (non only STM32, also for AVR), both the multiple cap albeit non polarized, e.g. 10n+1u in parallel

It's a really good question and many experienced designers understand this wrong, so wrong advice is commonly seen in datasheets, appnotes etc. Many also get this wrong on this very forum.

The idea is old, and back some decades ago 1uF capacitors were not available in small packages. Large package meant large equivalent series inductance (and, with some types, like electrolytics, also high ESR). This ESL+ESR sacrificed high-frequency performance (ability to supply very fast current changes). Small capacitor was added in parallel, in smaller case, enabling it to be closer to the load.

Nowadays you can get 1uF MLCC in 0402 package. If you parallel 1uF 0402 || 10nF 0402, you decrease the high frequency impedance only slightly, and this effect comes from having two capacitors with their package inductances acting in parallel, PCB traces and vias acting in parallel - not from having different capacitors. You could have used 1uF 0402 || 1uF 0402 (same part twice in parallel) to achieve the same HF performance, and better LF performance. Or just a single 1uF part with wider traces / more parallel traces, more vias than just one, etc.

People still show impedance plots to prove that smaller capacitance parts have higher SRF - the point where impedance is at lowest. They assume that paralleling different values results in overall combination of these lowest impedance points. What they miss is the absolute scale of the plots. If you compare 0402 1uF and 0402 10nF capacitors, and look at the frequency where the 10nF part has the lowest impedance, it is true that at the same point, the impedance of the 1uF cap has already significantly risen. But it started out lower, so it's still pretty much equal to the 10nF part - quite obviously, because the impedance beyond SRF is caused by the ESL, which is directly defined by the package and layout.

Target for bypassing is overall low impedance, and that is best achieved with a capacitor with zero physical size and infinite capacitance. In practice, because 100nF is sufficient for many ICs, and 1uF is sufficient for almost all ICs, and both are available in 0402 package smaller of which I would not recommend for hobbyists and small scale manufacturing for practical reasons, the choice is simple.

Paralleling different MLCC values increases the risk of inadvertently creating some weird resonance modes between the capacitors and layout inductance, so that's also one argument against the old, erratic appnote "advice". Although I don't think it's that common, those solutions usually work fine. But it's still needless BOM and design complication for not much if any gain.

Now, if you have a risk of parasitic LC oscillation, which can happen with long leads and large values of C, then adding even more C in a lossy form (electrolytic, or MLCC + explicit series resistor in parallel) helps dampen it, see https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf for example.

[tellurium]

I'd place a 1M resistor parallel to the crystal. This helps with startup especially when routing or part values are not optimal and has no drawbacks.

fchk

Could you elaborate more on that please?

[SiliconWizard]

Rookie question.

I've seen this weird stuff on some datasheet I've been reading (non only STM32, also for AVR), both the multiple cap albeit non polarized, e.g. 10n+1u in parallel

It's a really good question and many experienced designers understand this wrong, so wrong advice is commonly seen in datasheets, appnotes etc. Many also get this wrong on this very forum.

The idea is old, and back some decades ago 1uF capacitors were not available in small packages. Large package meant large equivalent series inductance (and, with some types, like electrolytics, also high ESR). This ESL+ESR sacrificed high-frequency performance (ability to supply very fast current changes). Small capacitor was added in parallel, in smaller case, enabling it to be closer to the load.

Nowadays you can get 1uF MLCC in 0402 package. If you parallel 1uF 0402 || 10nF 0402, you decrease the high frequency impedance only slightly, and this effect comes from having two capacitors with their package inductances acting in parallel, PCB traces and vias acting in parallel - not from having different capacitors. You could have used 1uF 0402 || 1uF 0402 (same part twice in parallel) to achieve the same HF performance, and better LF performance. Or just a single 1uF part with wider traces / more parallel traces, more vias than just one, etc.

People still show impedance plots to prove that smaller capacitance parts have higher SRF - the point where impedance is at lowest. They assume that paralleling different values results in overall combination of these lowest impedance points. What they miss is the absolute scale of the plots. If you compare 0402 1uF and 0402 10nF capacitors, and look at the frequency where the 10nF part has the lowest impedance, it is true that at the same point, the impedance of the 1uF cap has already significantly risen. But it started out lower, so it's still pretty much equal to the 10nF part - quite obviously, because the impedance beyond SRF is caused by the ESL, which is directly defined by the package and layout.

Target for bypassing is overall low impedance, and that is best achieved with a capacitor with zero physical size and infinite capacitance. In practice, because 100nF is sufficient for many ICs, and 1uF is sufficient for almost all ICs, and both are available in 0402 package smaller of which I would not recommend for hobbyists and small scale manufacturing for practical reasons, the choice is simple.

Paralleling different MLCC values increases the risk of inadvertently creating some weird resonance modes between the capacitors and layout inductance, so that's also one argument against the old, erratic appnote "advice". Although I don't think it's that common, those solutions usually work fine. But it's still needless BOM and design complication for not much if any gain.

Now, if you have a risk of parasitic LC oscillation, which can happen with long leads and large values of C, then adding even more C in a lossy form (electrolytic, or MLCC + explicit series resistor in parallel) helps dampen it, see https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf for example.

Agreed. Paralleling ceramic caps as described above is still very commonly seen, and is most often a kind of cargo cult designing based on usually not well-understood principles. While paralleling an electrolytic cap with a small ceramic cap made sense, the reason why is often a source of misconception.

As far as bypassing goes at least, paralleling a larger value (in the uF range) with a lower value (in the tens of nF range) of both ceramic SMD caps doesn't bring anything. Parasitic inductance and resistance is usually so low that it doesn't matter one bit. Where it could make a difference would be in niche cases - such as with RF filters for instance - but then all parameters of every capacitor and inductor you use would have to be carefully taken into account.

Now one reasonable reason for paralleling ceramic caps is to get a larger value not commonly available in individual SMD ceramic caps, as long as the ultra low resulting ESR doesn't cause issues in a particular circumstance. That's something I've routinely done with "modern" linear regulators which most often are perfectly stable even with input and output caps with extremely low ESR. Read your datasheets.

[Siwastaja]

Now one reasonable reason for paralleling ceramic caps is to get a larger value not commonly available in individual SMD ceramic caps, as long as the ultra low resulting ESR doesn't cause issues in a particular circumstance. That's something I've routinely done with "modern" linear regulators which most often are perfectly stable even with input and output caps with extremely low ESR. Read your datasheets.

Yes, it's an excellent idea to parallel same value of MLCCs. Large MLCC packages are more prone to cracking (due to board flex or even just thermal damage from poor soldering practices). Besides, often you need like 10uF somewhere and 4.7uF elsewhere. By just using 2x4.7uF in parallel, you can have just one BOM line.

[Bud]

Smaller MLCC packages have more capacitance drop under DC bias. Pick your poison.

[peter-h]

The reason for a 1M-10M res across the xtal is to provide a DC bias for the input of the amplifier.

Some oscillators need it, some don't, but if you are making an oscillator out of something like a 74HC inverter, you need to do that.