My first STM32 design

[ppTRN]

Hi everyone,
I started a couple weeks ago to dive into Kicad, migrating from Eagle. Since I have never worked with STM32 MCU's, I decided to design a simple dev board based on STM32F030K6T6 (choice dictated by the low price and LCSC availability). I plan to program the board with an ST-LINK V2. The board includes the MCU, USART-USB bridge, power supply and acces to most of the MCU's pins.

Let me know what you think about the design and the routing, especially in the USB plug part, where the dimensions didn't allowed me to set the proper trace width for a 90Ohm impedence, but the traces are simmetrical and lenght matched. I am unsure tho about the D+ and D- interconnections in the plug.

Soon enough, i hope this evening or tomorrow (italian time), you'll find on the KiCad section of this forum my consideration about starting to use KiCad.

As always thanks for you precious opinions and suggestions.

Ps: the pcb have 4 layer, SIGNAL-GND-3V3-MIXED

[voltsandjolts]

Well, that looks very neat and tidy, well done.
Slide switches seem a bit of an odd choice, rather than momentary, but maybe you have them already.
Maybe add some ESD protection on VEXT for benefit of Q1.
Don't worry about USB DP/DM routing, its only 12MHz FS so it'll be fine.

[ppTRN]

Thanks. I won't actually use dip switches. I have some regular switches here at home, and the footprint of those dip switches matches just fine, i will use those

[Jope]

Instead of the STM32F030, I would have used a STM32F070, which includes a USB peripheral and would have made the CP2102 unnecessary.

[coromonadalix]

And sorry to barge in, i would not use an cp2102

There was some compatibility problems on win10

I would try an mcu with the integrated peripheral as written  or other CPXXXX  devices who are certified  for any OS ...

[Jeroen3]

There are currently no problems with the cp2102, we're using them extensively.

Doing your own usb stack, getting vid/pid and your driver signed is a lot more work!

[fchk]

I'd place a 1M resistor parallel to the crystal. This helps with startup especially when routing or part values are not optimal and has no drawbacks.

fchk

[ppTRN]

Of course an MCU with native USB would have been the more logic solution, but the USB bridge is more of an experiment than a need. I'll se when I'll assemble the board of it gives me any problems (it wasn't even cheap, at 2.5$ a piece). The 1M resistor in parallel to te quartz is actually new to me, i'll make sure to add it to the next design!

[Siwastaja]

If all you need is UART over USB then obviously a dedicated chip saves a lot of software development work, this is valuable when you want to concentrate on something else than USB implementation.

CP2102 is fine, every USB-UART bridge have had issues in past.

Design seems quite fine, even a tad overengineered. I would have probably done it in two layers, and without weird stuff like many different bypass cap values, LC filtering of ADC supply and so on. By handwaving all this together, this poses a risk of making things worse than a simpler design, with of course an opportunity to make things better. But nah, even if it's "worse", it will work fine for the intended use.

[SiliconWizard]

+1 for the bypass caps. There is usually no good reason these days to use a polarized 10µF cap and a ceramic cap in parallel as you did. Although the schematic suggests that, but I'm not sure I see any polarized cap on the layout? I may have missed it. Anyway, absolutely useless. Use a single 10uF ceramic cap instead.

I would also second the fact a 4-layer PCB here is overkill, but that's your call. It certainly won't harm.

[Siwastaja]

The only place where the polarized, larger capacitor is useful is the power supply input (Vbus). Not because of polarization, but because of the ESR of electrolytic capacitor, which helps dampen possible oscillations or hotplug overshoot which you can have if you have large MLCC in the input directly, as shown. Although the series resistance of F1 might already solve any such issue. And the fact that AMS1117 won't blow up at 6V.

Also possibly useful in that CLC filter; if you make the filter lossy (either by lossy C's, lossy L, or both), you reduce risk of filter resonances.

So it seems all the polarized caps are in the "wrong" places (C1, C12); I would remove them (not replace with large MLCCs, the 100n caps are fine alone); then I would add a 47-100uF elcap in parallel with C7. Then I would remove L1 and C5. Only if I'm sure that I need LC filtering on VDD_A, then I would look at lossy ferrite bead which does not saturate under I_vdda, or possibly parallel resistor with L, or replace C5 with a 4.7uF tantalum cap, and add another such tantalum in parallel with C4. But even this is handwaving; modeling it properly is a lot of work. Better just start out simple.

That said, the circuit will probably work perfectly as shown.

Most important key points, use small package SMD MLCC at each power pin. The more capacitance the better as long as it does not increase package size; 100nF is considered minimum, 1uF does not hurt as long as it's small. Use same part at each pin, no "paralleled different values" trickery. Then use electrolytic bulk capacitance at Vin. That's about it.

[SiliconWizard]

Where low ESR is a concern, you can add a small series resistor to a ceramic - still much cheaper and potentially more reliable while taking up less space. That's what I tend to do these days and keep electrolytic (or tantalum) for cases where the required capacitance is much too high to be practical with ceramic. But I don't see this justified for this particular design.

[ppTRN]

Thank you all for the advices, the design is not definitive, so i might change stuff according to your suggestions

[peter.lu]

Only one tip

The STM32F030's flash erase times is 1k.

[peter.lu]

Another question

Why use a four layer PCB layout？ What is your consideration？

[Siwastaja]

Where low ESR is a concern, you can add a small series resistor to a ceramic - still much cheaper and potentially more reliable while taking up less space. That's what I tend to do these days and keep electrolytic (or tantalum) for cases where the required capacitance is much too high to be practical with ceramic. But I don't see this justified for this particular design.

The situation for electrolytics is when you need large amount of low-ESR capacitance, for example a 10uF MLCC, and then you need to damp it. You can of course do it with another MLCC + explicit series R, but for the damping to be effective, the capacitance needs to be at least 2-3 times the low-ESR capacitance, so it's getting big. Then again, big MLCC packages have a risk of cracking, so you would end up reusing the already existing 10uF MLCC, three in parallel, plus the resistor, four components taking up even more space. This is where I just slap a 47µF electrolytic cap.

But of course, even just 10uF MLCC || (10uF MLCC + resistor) offers some damping, maybe that is enough. One can always measure.

[ppTRN]

Why use a four layer PCB layout？ What is your consideration？

The only reason is that right now, for such board dimension, the cost of production by JLCPCB is the same for a 2 layer board.

Only one tip

The STM32F030's flash erase times is 1k.

That is surely a problem for a dev board, thanks

Most important key points, use small package SMD MLCC at each power pin. The more capacitance the better as long as it does not increase package size; 100nF is considered minimum, 1uF does not hurt as long as it's small. Use same part at each pin, no "paralleled different values" trickery. Then use electrolytic bulk capacitance at Vin. That's about it.

May I ask why the small package is important?

[Siwastaja]

May I ask why the small package is important?

Yes,

the whole point in bypass caps is they respond to the quickly varying need for current of the ICs. But rate of current change is physically limited by the inductive impedance of the wiring. When the IC demands more current suddenly, e.g. switches an output pin, supply voltage seen by the IC drops by dV = Z*dI. And because this is reactance and not just resistance, when the IC has done its job charging the internal (or external IO) capacitances and suddenly consumes less current, opposite voltage (exceeding the supply voltage!) is generated by the wiring inductance. In other words, wiring inductance robbed the IC from some voltage and paid it back.

An MCU rated for Vcc=3.3V of course can function even if Vcc goes down to 3.2V and then up to 3.4V. All you can do is to minimize supply inductance and this is why a bypass capacitor is used in the first place. By using a small package, the capacitive element itself will be closer to the IC, and equivalent series inductance will be smaller. One could theoretically model all of this, but it is less effort to do one's best handwaving the "best practices" type of thing.

Anyway, capacitance itself is a secondary parameter; as long as you have enough, excess does not matter. So you choose bypass caps for smallest possible inductance. Inductance of MLCC then again is only dependent on the package size, nothing else, so it even isn't a datasheet parameter. Inductance is simply caused by the inductive loop that results in from the physical loop that is inevitably formed by the component footprint. You can reduce this impedance by using multiple vias into the ground plane instead of just 1, and so on. And of course, a larger part simply won't fit right next to the IC (you have to break it out further away so you have room to route other pins!), while a smaller one does. This makes a much bigger difference than the ESL of the capacitor itself.

Practically, an STM32 is not a hugely challenging IC. It will probably function fine with a 0805 capacitor 10mm away from the Vcc pin, even though a 0402 capacitor 1mm from the pin would be better.

[peter-h]

It's an interesting point whether a separate USB-serial chip is worth using, versus a CPU which can do USB VCP (and USB other stuff) internally.

Fewer chips = a good thing.

The one used here will self install under win7 or later so no need to ship a driver, but I am not sure whether the ST one will self install.

[SiliconWizard]

The benefit of using a dedicated USB interface chip is that it's a purely "hardware" solution with no firmware involved for the USB implementation. Saves both code memory and potential bugs. Drivers can also be a concern depending on OS and OS version.

And this is a simple dev board mostly meant as an exercise for the OP as far as I can tell.

That said, an amusing remark. The CP2102N is currently more expensive than the FT230X (by about 60%!) - it used to be significantly cheaper than FTDI parts a few years back.

[Doctorandus_P]

With a uC and built in USB peripheral you can use it as a CDC (Communication Device Class) device and use standard drivers. I never have to worry about those things, as I run Linux, but I think this should work on windoze too.

When the USB peripheral is integrated, you also do not have to worry about setting baudrates and other "serial" parameters, as there is no physical serial interface. You can also use other device classes such as mass storage or HMI.

I have not done much with STM32, but I did once did put serial_sathosimn (from github) into a "Blue Pill" and did a few short tests with it. It created 3 extra serial ports on my linux box.

[peter-h]

I have USB VCP (CDC) and MSC (2MB FAT12 via FatFS) and it works fine. 32F417.

What I can't tell you right away is whether windows auto installs the driver or whether you have to provide the driver to windows.

[peter-h]

Got more info on the ST USB VCP driver:

The VCP driver auto installs for Windows above win7. For win7 the ST “driver” can be used:



If you look at the .inf file you’ll see the VID/PID used. The cat file is simply a compiled, cross-signed version of the inf file. There is no actual driver here, it is just a signed connection between the VID/PID and the standard Microsoft CDC driver. This gets around the problem that, for some reason, Microsoft didn’t associate their default driver with the USB class type (CDC) in the same way as they do for other generic USB classes (e.g. MSC, HID etc). In Windows 10 they finally fixed this problem so a cross-signed cat file is no longer required for CDC devices.

For Linux/FreeBSD/MacOS a driver has never been needed as Linux/FreeBSD/MacOS (in fact everything other than Windows before Win10) all recognise the CDC class and use the correct built-in driver much as they do for other standard USB classes such as HID (keyboards/mice) or MSC (mass storage). Before Win10, Windows, for some reason, needed an inf file to associate the VID/PID with its built-in CDC driver instead of recognising the class ID.

The advantage of an FT232 is that you get VCP support all the way back to win95. With later FT parts it is win7 onwards only (possibly XP embedded). With the chip proposed here, I don't know. XP is still heavily used in industrial control.

[uliano]

I would have probably done it in two layers, and without weird stuff like many different bypass cap values, LC filtering of ADC supply and so on.

Rookie question.

I've seen this weird stuff on some datasheet I've been reading (non only STM32, also for AVR), both the multiple cap albeit non polarized, e.g. 10n+1u in parallel and some sort of filtering of analog supply albeit by ferrite beads and not by inductance (not sure even what the difference is among these two).

why are these stuff causing more troubles than solving problems and if so why I keep finding them in datasheets even from different producers?

[peter-h]

It is common to use an electrolytic/tantalum cap in parallel with a ceramic one, because the former gives you high capacitance (but high ESR) and the latter gives you low ESR.

I am pretty sure the inductors often do nothing but people put them in because 40 years ago they saw a data sheet showing them They are often not that cheap, either, and can suddenly go on a long lead time.

[Siwastaja]

Rookie question.

I've seen this weird stuff on some datasheet I've been reading (non only STM32, also for AVR), both the multiple cap albeit non polarized, e.g. 10n+1u in parallel

It's a really good question and many experienced designers understand this wrong, so wrong advice is commonly seen in datasheets, appnotes etc. Many also get this wrong on this very forum.

The idea is old, and back some decades ago 1uF capacitors were not available in small packages. Large package meant large equivalent series inductance (and, with some types, like electrolytics, also high ESR). This ESL+ESR sacrificed high-frequency performance (ability to supply very fast current changes). Small capacitor was added in parallel, in smaller case, enabling it to be closer to the load.

Nowadays you can get 1uF MLCC in 0402 package. If you parallel 1uF 0402 || 10nF 0402, you decrease the high frequency impedance only slightly, and this effect comes from having two capacitors with their package inductances acting in parallel, PCB traces and vias acting in parallel - not from having different capacitors. You could have used 1uF 0402 || 1uF 0402 (same part twice in parallel) to achieve the same HF performance, and better LF performance. Or just a single 1uF part with wider traces / more parallel traces, more vias than just one, etc.

People still show impedance plots to prove that smaller capacitance parts have higher SRF - the point where impedance is at lowest. They assume that paralleling different values results in overall combination of these lowest impedance points. What they miss is the absolute scale of the plots. If you compare 0402 1uF and 0402 10nF capacitors, and look at the frequency where the 10nF part has the lowest impedance, it is true that at the same point, the impedance of the 1uF cap has already significantly risen. But it started out lower, so it's still pretty much equal to the 10nF part - quite obviously, because the impedance beyond SRF is caused by the ESL, which is directly defined by the package and layout.

Target for bypassing is overall low impedance, and that is best achieved with a capacitor with zero physical size and infinite capacitance. In practice, because 100nF is sufficient for many ICs, and 1uF is sufficient for almost all ICs, and both are available in 0402 package smaller of which I would not recommend for hobbyists and small scale manufacturing for practical reasons, the choice is simple.

Paralleling different MLCC values increases the risk of inadvertently creating some weird resonance modes between the capacitors and layout inductance, so that's also one argument against the old, erratic appnote "advice". Although I don't think it's that common, those solutions usually work fine. But it's still needless BOM and design complication for not much if any gain.

Now, if you have a risk of parasitic LC oscillation, which can happen with long leads and large values of C, then adding even more C in a lossy form (electrolytic, or MLCC + explicit series resistor in parallel) helps dampen it, see https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf for example.

[tellurium]

I'd place a 1M resistor parallel to the crystal. This helps with startup especially when routing or part values are not optimal and has no drawbacks.

fchk

Could you elaborate more on that please?

[SiliconWizard]

Rookie question.

I've seen this weird stuff on some datasheet I've been reading (non only STM32, also for AVR), both the multiple cap albeit non polarized, e.g. 10n+1u in parallel

It's a really good question and many experienced designers understand this wrong, so wrong advice is commonly seen in datasheets, appnotes etc. Many also get this wrong on this very forum.

The idea is old, and back some decades ago 1uF capacitors were not available in small packages. Large package meant large equivalent series inductance (and, with some types, like electrolytics, also high ESR). This ESL+ESR sacrificed high-frequency performance (ability to supply very fast current changes). Small capacitor was added in parallel, in smaller case, enabling it to be closer to the load.

Nowadays you can get 1uF MLCC in 0402 package. If you parallel 1uF 0402 || 10nF 0402, you decrease the high frequency impedance only slightly, and this effect comes from having two capacitors with their package inductances acting in parallel, PCB traces and vias acting in parallel - not from having different capacitors. You could have used 1uF 0402 || 1uF 0402 (same part twice in parallel) to achieve the same HF performance, and better LF performance. Or just a single 1uF part with wider traces / more parallel traces, more vias than just one, etc.

People still show impedance plots to prove that smaller capacitance parts have higher SRF - the point where impedance is at lowest. They assume that paralleling different values results in overall combination of these lowest impedance points. What they miss is the absolute scale of the plots. If you compare 0402 1uF and 0402 10nF capacitors, and look at the frequency where the 10nF part has the lowest impedance, it is true that at the same point, the impedance of the 1uF cap has already significantly risen. But it started out lower, so it's still pretty much equal to the 10nF part - quite obviously, because the impedance beyond SRF is caused by the ESL, which is directly defined by the package and layout.

Target for bypassing is overall low impedance, and that is best achieved with a capacitor with zero physical size and infinite capacitance. In practice, because 100nF is sufficient for many ICs, and 1uF is sufficient for almost all ICs, and both are available in 0402 package smaller of which I would not recommend for hobbyists and small scale manufacturing for practical reasons, the choice is simple.

Paralleling different MLCC values increases the risk of inadvertently creating some weird resonance modes between the capacitors and layout inductance, so that's also one argument against the old, erratic appnote "advice". Although I don't think it's that common, those solutions usually work fine. But it's still needless BOM and design complication for not much if any gain.

Now, if you have a risk of parasitic LC oscillation, which can happen with long leads and large values of C, then adding even more C in a lossy form (electrolytic, or MLCC + explicit series resistor in parallel) helps dampen it, see https://www.analog.com/media/en/technical-documentation/application-notes/an88f.pdf for example.

Agreed. Paralleling ceramic caps as described above is still very commonly seen, and is most often a kind of cargo cult designing based on usually not well-understood principles. While paralleling an electrolytic cap with a small ceramic cap made sense, the reason why is often a source of misconception.

As far as bypassing goes at least, paralleling a larger value (in the uF range) with a lower value (in the tens of nF range) of both ceramic SMD caps doesn't bring anything. Parasitic inductance and resistance is usually so low that it doesn't matter one bit. Where it could make a difference would be in niche cases - such as with RF filters for instance - but then all parameters of every capacitor and inductor you use would have to be carefully taken into account.

Now one reasonable reason for paralleling ceramic caps is to get a larger value not commonly available in individual SMD ceramic caps, as long as the ultra low resulting ESR doesn't cause issues in a particular circumstance. That's something I've routinely done with "modern" linear regulators which most often are perfectly stable even with input and output caps with extremely low ESR. Read your datasheets.

[Siwastaja]

Now one reasonable reason for paralleling ceramic caps is to get a larger value not commonly available in individual SMD ceramic caps, as long as the ultra low resulting ESR doesn't cause issues in a particular circumstance. That's something I've routinely done with "modern" linear regulators which most often are perfectly stable even with input and output caps with extremely low ESR. Read your datasheets.

Yes, it's an excellent idea to parallel same value of MLCCs. Large MLCC packages are more prone to cracking (due to board flex or even just thermal damage from poor soldering practices). Besides, often you need like 10uF somewhere and 4.7uF elsewhere. By just using 2x4.7uF in parallel, you can have just one BOM line.

[Bud]

Smaller MLCC packages have more capacitance drop under DC bias. Pick your poison.

[peter-h]

The reason for a 1M-10M res across the xtal is to provide a DC bias for the input of the amplifier.

Some oscillators need it, some don't, but if you are making an oscillator out of something like a 74HC inverter, you need to do that.