Author Topic: PLD Design Software  (Read 10407 times)

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Offline davec

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PLD Design Software
« on: August 25, 2013, 08:43:30 pm »
Let me start by offering my apologies if this is a stupid question.

I'm working on a circuit with a lot of 5V TTL logic and various parts which needs to remain 5V TLL logic. However, I'm wondering if I can replace an assortment of 74 series chips with a few PLD devices. I'd rather stay away from surface mount and 3.3V or lower, which I know limits my options.

I've been looking at using some 22V10 or 16V8, they sounds like they should do the job. I've got some Atmel ATF22V10CQZ and ATF16V8CZ chips which my Mini Pro USB Programmer claims to support.

The only software I can find is Win Cupl, I was sort of expecting to be able to drag a drop a selection of gates, counters, flip flops etc. wire them all up and burn that into the chip. Is there something like that, or have I totally missed the mark?

I suppose by the time people started writing software like that, PALs and GALs were old technology. In which case, is there some different technology I need to look at, something where I can draw out the logic and then get that down to some silicon, ideally 5V tolerant and in a DIL package? (and it doesn't need microcontroller in this case, it's just glue logic).

Thanks,

Dave
 

Offline fcb

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Re: PLD Design Software
« Reply #1 on: August 25, 2013, 08:48:37 pm »
XC9500 series still available in 5v.

But you should defiantly make the effort with 3v3 - it's not going away.
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Offline marshallh

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Re: PLD Design Software
« Reply #2 on: August 25, 2013, 08:50:17 pm »
Yes, WinCUPL will do the job. You write CUPL language files that are basically logic descriptions of the pins involved.
You can write intermediate expressions using boolean logic.
It's like very bare bones verilog.
It generates a JED programmer file which you burn to the 22V10 then.
Using this method I made a simple 4-bit CPU out of about 5 GALs.

If you really have to have graphcial schematic support, your best bet is Xilinx ISE, and the XC9500 series CPLDs. They are EOL now but you can still buy them.

If you have a lot of logic to be replaced, it may be more practical to use a somewhat modern 3.3v CPLD and level translation where necessary.
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Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #3 on: August 25, 2013, 09:08:35 pm »
Schematic entry is very limiting - CUPL is a straightforward language to learn and much more powerful.
You can express in a few lines what would be a pretty messy schematic.
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Offline davec

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Re: PLD Design Software
« Reply #4 on: August 25, 2013, 09:15:13 pm »
I guess I need to read up on CUPL then, just wanted to make sure I wasn't missing something obvious.

I don't have anything against lower voltages, it's just this is part of an existing system which needs to stay 5v.

It's about 20-30 74 series chips, so probably not worth the effort level shifting in and out of a CPLD.

Thanks,

Dave
 

Offline free_electron

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Re: PLD Design Software
« Reply #5 on: August 26, 2013, 04:59:47 am »
ABEL , PALASM. they should do the trick.
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Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #6 on: August 26, 2013, 08:05:14 am »
Not used ABEL but PALASM is very crude (unless it;s been enhanced a lot since I used it 25-odd years ago) - like using assembler vs. C on a microcontroller.
I think Atmel still provide free WinCUPL for their devices. ISTR the full version of DOS CUPL used to cost £1000+ in its day
 
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Offline westfw

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Re: PLD Design Software
« Reply #7 on: August 31, 2013, 07:36:43 am »
Quote
I was sort of expecting to be able to drag a drop a selection of gates, counters, flip flops etc. wire them all up and burn that into the chip.
Tools aside, you're expecting a lot from a 22v10-class chip.  It only has 10 flip-flops, all with a common clock, and one level of and/or array.  One chip will replace several logic chips, or perhaps a couple of small counters (up to 10bits total), but you aren't going to be able to make one into, say, a 4-digit 7-segment multiplexed display driver...

I don't suppose there's a collection of 22v10/16v8/etc designs cover various boring and/or particularly clever uses of the chips?  There are various sites for more complex configurable logic, but I don't think I've seen anything for the simpler chips...
 

Offline free_electron

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Re: PLD Design Software
« Reply #8 on: August 31, 2013, 11:53:01 am »
A 22v10 is essentially 10 flipflops...

You may want to fish for the old intel pld's ( sold to altera ) like the 610 and 910. Those were 28 and 40 pin dil packages and up to 128 flipflops. They were essentially 4 or 8 20v10's in a package with interconnect between them.

The older quartus software supports them.
There you can draw schematics.
The old max7000 family is still around. Those are available in plcc package up to 84 pins... Slap em in a thru hole socket and bob's your uncle.... Make sure to get the -S version so you can reprogram them !
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Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #9 on: August 31, 2013, 12:04:20 pm »
A 22v10 is essentially 10 flipflops...

You may want to fish for the old intel pld's ( sold to altera ) like the 610 and 910. Those were 28 and 40 pin dil packages and up to 128 flipflops. They were essentially 4 or 8 20v10's in a package with interconnect between them.

The older quartus software supports them.
There you can draw schematics.
The old max7000 family is still around. Those are available in plcc package up to 84 pins... Slap em in a thru hole socket and bob's your uncle.... Make sure to get the -S version so you can reprogram them !

There are also some nicer devices like the Altera EP600, which ISTR had more buried (non pin-specific) macrocells and T type flip flops for efficient counter implementation. Atmel's ATV750 and 2500 were also more complex devices, but I suspect modern cheap CPLDs would be way better unless you really needed 5V and/or DIP.
I also recollect that  PEEL devices had some interesting features that made them more useful than similar sized GALS - I think it was the ability fo feed a macrocell output back as an input for buried logic and also use its pin as an input at the same time. Or was it individual macrocell clocks... memory is hazy!
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Offline free_electron

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Re: PLD Design Software
« Reply #10 on: August 31, 2013, 01:31:37 pm »
Peel's have foldback from out to in.
The. Altera 600 was originally an intel device.
300 310 600 610 900 910 were intel pld's. that division was sold to altera . Its direct offspring is the max family.
AMD did the same with their Mach devices. Mach 200 210 400 410 .. See a pattern there ?
Intel sold to altera, amd sold to lattice. MMI was inventor of Pal, fabbed at ti, Lattice was the inventor of GAL. They fabbed at ST.

This architecture later became what is now known a CPLD.

Essentially a bunch of PAL (MMI trademark) or GAL (ST / lattice trademark) on a same die with an additional i terconnect matrix between em.

A pal or gal is essentially a gatecloud , possibly followed by registers. (Not all pals have fliplflops , they can be pure and/ or / not clusters)
As a reult there is no, or very limited(gal/peel) feedback from the last output to the interconnect matrix. the cluster outputs connect to the pin of the chip.
Cplds solve that problem by having an additional interconnect matrix between the cloud output and the pins.
In a pal or gal the cloud output goes directly to a, fixed, pin. You can't reroute output 7 to pin 3... Some adjacent pin swaps are possible but it is not truly random. Cplds solve that by having an interconnect grid between the clouds and the outputs.

In simple pld's there is one flipflop per pin. So a 40 pin device could have 32 flipflops (basically four pal's. a pal thpically had either none, 4 or 8 flipflops). There were no buried flipflops.
Cpld allowed buried flipflops. Essentially a pal that is not routed to io

Hierarchy( complexitiy)

Combinatorial pal. And or not only, no feedback
Registered pal. Adds Registers, no feedback
Gal .reprogrammable (pal is OTP)
Peel feedback
Pld . Cloud of pals. Interconnect on input, feedback , but no interconnect on output. One flipflop per pin
Cpld , cloud of pals , interconnect on input and output, buried pals (more flipflops than pins.)

The problem with such an architecture is that it is extremely wasteful. The routing is so limited and you waste too much logi in the combinatorial cloud. The granularity is too high.

Fpga solves that. There the combinatorial cloud is smaller and there are only 2 or 4 flipflops per block.
This is called a macrocell. You can see a macrocell as half a peel. Basically 2 or 4 flipflops with feedback into the matrix. Then there are short interconnects between adjacent macrocells, intermediates that hop 2 or 4 macrocells far. This makes a cluster of macrocells called macroblock.
A large interconnect grid then connects neighbouring macroblocks 1 2 or 4 hops. Macroblocks are arranged in stripes vertically or horizontally. The you have large raceways interconnecting the columns

Waferscale took the cpld and slapped on ram and eprom eeprom to essentially make the ipsd.
Take cpu of choice, config the logic to do address decoding and io and some simple functions. Load code in eeprom and go. Two chip solution. Cpu and an ipsd.

All gone the way of the wind ... I had an mmi databook in 1986.. The software was a 51/4 inch 360 floppy for dos.
You had to make a textfile with stars and dots. A star was a blown fuse.... They had drawings with rows and columns..
It was like orcad for dos making linrary symbols with the star and dot thingie....

Meanwhile Actel came up with the pga programmable gate array. This was antifuse technology for the military. Xilinx replaced the antifuse with ram and fpga was born...
Altera kickstarted due to intel seeding them their cpld line
The xilinx tools originally were. Schematic entry. Viewdraw and viewlogic on early sun workstations.
Altera used daisycad as an entry tool.
Orcad stepped in the pal and gal config with orcad pld...

Wow... Talk about a trip down memory lane.....
Now kids come out of school barely know what is a nand gate, let alone knowing you can have four of those in a 7400 ttl chip... They stare at you .:Wtf is a ttl ? Vhdl we have heard of ...
« Last Edit: August 31, 2013, 01:50:15 pm by free_electron »
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Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #11 on: August 31, 2013, 01:50:12 pm »
As a reult there is no, or very limited(gal/peel) feedback from the last output to the interconnect matrix. the cluster outputs connect to the pin of the chip.
My recollection is you clould always feed back, but in PAL/GALs only if it was driving a pin, so you couldn't use the pin as an input, and couldn't hide internal state to prevent reverse engineering.
I think on older PAL xxRx devices There was the complication of a global output enable for registered ouputs.
..but in those days we were grateful for anything we could get, however limited. And of course no in-circuit programming (but it was pretty much all DIL so not a big deal).
PALs were OTP (real fuses that actually got phyically blown) , GALS were reprogrammable but not in-circuit until very late onwith the Lattice ISPGALs, which never really caught on as CPLD type devices were coming in by then.
ISTR using Cypress (?) UV erasable PAL equivalent devices for prototyping PAL designs - I think I even built a programmer for them.

 
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Offline free_electron

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Re: PLD Design Software
« Reply #12 on: August 31, 2013, 01:56:24 pm »
Yep, cypress had uv erasble pals. That was their contribution.
There were other weirdos on the market like quicklogic , actel, atmel , at&t (the orca family).

Yes. Feedback was only from pin. No buried feedback possible. Peel changed that.

I have some pals and gals still laying around somewhere... I think even uv erasable ones. Intel had uv versions for their pld and cpld. The palstic ones were otp.
The intel devices were programmed with 4 wires and a printerport. It wasnt exactly jtag, but close). Pal and gal needed a bit more crap to do it , until iscpal and icsgal from lattice came along.

I had the pal gal programmer from elektor. Later i bought a data io chiplab. That thing could program anything.

Pals initially could be copied. They had no fusebits.. Gals had fusebits from the get-go. Dont know if pals ever got fuse bits.

Ahhh memories....
« Last Edit: August 31, 2013, 01:58:32 pm by free_electron »
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Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #13 on: August 31, 2013, 02:50:51 pm »
Pals initially could be copied. They had no fusebits.. Gals had fusebits from the get-go. Dont know if pals ever got fuse bits.
I think the PAL16L8/R4/R6/R8 had protect fuses, but not very useful as the lack of buried outputs means you could pretty much always deduce the contents by excersising & observing. I vaguely recollect a college paper describing an automated process for this.
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Offline nctnico

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Re: PLD Design Software
« Reply #14 on: August 31, 2013, 02:53:24 pm »
IIRC I have used PALASM in the past. It could simulate and optimise. For small devices like the GAL16V8 or GAL20V10 this is all you need. Just punch in the logic equations and the software optimises them. IMHO its still a good start to get into programmable logic and there is definitely a use for programmable logic in simple circuits. If you go a step further (from Programmable Array Logic to CPLD) then VHDL or Verilog may be a better choice.
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Re: PLD Design Software
« Reply #15 on: August 31, 2013, 03:35:40 pm »
Later i bought a data io chiplab. That thing could program anything.

I bagged a load of Peel devices the other year from Ebay for a couple of pounds and then a cheap Chiplab.
The software for those was (ahem, cough is ;-) winPLACE     The second image shows the macrocell options that can be found in the 18CV8, which is the chip I picked from the menu.

I know this stuff is mostly considered old crap now, but as a beginner I think it's important to at least know of, the evolution of stuff as it makes more current things like FPGA's and Quartus II etc easier to understand.


[edit: sry added the correct pic]
« Last Edit: August 31, 2013, 03:40:03 pm by jucole »
 

Online andersm

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Re: PLD Design Software
« Reply #16 on: August 31, 2013, 06:30:08 pm »
There was a post on Atmel's blog recently describing their current SPLD and CPLD offerings.

Offline westfw

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Re: PLD Design Software
« Reply #17 on: September 01, 2013, 12:22:05 am »
Quote
Feedback was only from pin. No buried feedback possible.
Unless I'm misreading it, the Lattice 22v10 datasheet shows feedback from the Q/ outputs of the flipflops, independent of whether the Q outputs are connected to pins...
 

Offline marshallh

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Re: PLD Design Software
« Reply #18 on: September 01, 2013, 01:47:37 am »
IIRC only the L series pal/gals are combinational-only. The R and V types can have I/O connects optionally killed off and the registers fed back to internal logic.

You can't easily reverse them because they can depend on a stored state.
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Offline westfw

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Re: PLD Design Software
« Reply #19 on: September 01, 2013, 05:21:47 am »
(The GAL/PEEL claim to fame was that they could replace both PALnnRm chips (with registers) and PALxxLy chips (wholly combinatorial), wasn't it?  Minor other improvements (outputs could be inputs), plus re-programmable, but I thought the big thing was cutting the number of chips you had to stock.  Even the 16R8 appears to have feedback from the register outputs (you can't do counters or shift registers without it, can you), but it gives up having the Outputs double as inputs to make that possible.  (both 16r8 and 16l8 have 32x64 AND arrays.))

I'd still love to find a collection of PAL/GAL sample designs.  A bit of web searching didn't turn up anything more than a couple of examples from engineering classes (gray-scale counter, 7-segment decoder...)
I can contribute a classic LED "scanner", but that was as close to GAL logic as I've ever gotten, as a "programmer."
 

Offline jeroen74

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Re: PLD Design Software
« Reply #20 on: September 01, 2013, 10:50:07 am »
Elektor long ago (late eighties, early nineties) published a book on GAL programming that contains more then the trivial standard examples.
 

Offline mikeselectricstuff

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Re: PLD Design Software
« Reply #21 on: September 01, 2013, 09:49:04 pm »
(The GAL/PEEL claim to fame was that they could replace both PALnnRm chips (with registers) and PALxxLy chips (wholly combinatorial), wasn't it?  Minor other improvements (outputs could be inputs), plus re-programmable, but I thought the big thing was cutting the number of chips you had to stock.  Even the 16R8 appears to have feedback from the register outputs (you can't do counters or shift registers without it, can you), but it gives up having the Outputs double as inputs to make that possible.  (both 16r8 and 16l8 have 32x64 AND arrays.))

I'd still love to find a collection of PAL/GAL sample designs.  A bit of web searching didn't turn up anything more than a couple of examples from engineering classes (gray-scale counter, 7-segment decoder...)
I can contribute a classic LED "scanner", but that was as close to GAL logic as I've ever gotten, as a "programmer."
Wincupl comes with quite a few examples - I've attatched them in a zip
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