need high resolution PWM

[PCB.Wiz]

I'll definitely try that, as i2s naturally gives me enough resolution, and the chip seems to be DC capable. The power stage is closed loop, which is my major concern as the loop is certainly not tuned to drive an ultra low impedance load.

Thinking more about that any-load dictate, you may be better to move from Audio-stages which seem to have just under 100 mΩ, to a much 'stiffer' sync SMPS design.

And it would cost more than linear regulation with a big MOSFET and heatsink.

I'm not so sure. Power dissipation would be 5A x 15V30V = 75W150W meaning substantial heat sink and probably fan. And power consumption also doubles requiring a bigger PSU brick.

That original 30V raw power has to come from somewhere, usually the AC mains.
So you modulate that upstream power supply to give just the voltage you need, to run a linear regulator, thus slashing the linear-stage watts.

But try to get a linear amplifier drive a 1 milliohm load - this is a really challenging task. That's why my plan is to achieve enough "stiffness" in the H bridge itself, which should allow me to reduce feedback gain. And I should even be able to live with nonlinearity, because the system uses frequency analysis.

That infers you need very good current control, as a deviation of just 5mV into that 1mΩ* ohm load, hits your 5A current limit.

* You must also have exceptionally short leads

[tatus1969]

Thinking more about that any-load dictate, you may be better to move from Audio-stages which seem to have just under 100 mΩ, to a much 'stiffer' sync SMPS design.

I had looked into the TAS3251 datasheet, and that number actually ended that route.

That original 30V raw power has to come from somewhere, usually the AC mains.
So you modulate that upstream power supply to give just the voltage you need, to run a linear regulator, thus slashing the linear-stage watts.

As the system operates in two quadrants (both sinking and sourcing AC and DC current), this would need two (two-quadrant capable) DCDC's with the linear stage sandwiched between them...

That infers you need very good current control, as a deviation of just 5mV into that 1mΩ* ohm load, hits your 5A current limit.
* You must also have exceptionally short leads

The system uses a 4-terminal connection. The (all digital) control loops in the demonstrator have already shown that they maintain stability even when shorting the outputs with crocodile clips (after voltage sensing). That's probably in the order of 1milliohm. But I have an additional fast current supervisor that would kick in otherwise. The only problems that I see at the moment are DAC resolution and a stiff yet cost effective power stage.

[dmendesf]

I had this problem with the ADCs... If I Started them one after the other I got a few degrees of phase delay between them. Solved it by disabling the ADC clock, enabling the ADCs and then enabling the ADCs clocks.

Enviado de meu moto g(6) plus usando o Tapatalk

[PCB.Wiz]

The only problems that I see at the moment are DAC resolution and a stiff yet cost effective power stage.

Sync SMPS are inherently two quadrant if driven in fixed PWM mode, so you just need to find low mOhm Dual MOSFETS, and a matching driver.

HP8S36TB   Rohm is a good price at $0.56270/1k but is 30V rated ( DUAL 30V    2.4 mOhm @ 32A, 10V)

Infineon have Audio class D pre-drivers that use external MOSFETS with choice of Audio or PWM in, but there are many SMPS drivers out there.... ?

[Yansi]

International rectumfryer  also has some interesting ones.. (IRS2092, etc...)

[tatus1969]

I had this problem with the ADCs... If I Started them one after the other I got a few degrees of phase delay between them. Solved it by disabling the ADC clock, enabling the ADCs and then enabling the ADCs clocks.

Thanks, I'll try this out!

Sync SMPS are inherently two quadrant if driven in fixed PWM mode, so you just need to find low mOhm Dual MOSFETS, and a matching driver.

Sure, but two DCCM SMPS plus an analog amplifier is too much in terms of BOM and cost. I plan to fulfill all requirements with a single power stage. Thanks to all your support I will make the first attempt with CS4334-KSZ (24bit audio DAC), sigma delta modulation, and my own proprietary H bridge topology that (if my idea works) will eliminate switching deadtime entirely.

Infineon have Audio class D pre-drivers that use external MOSFETS with choice of Audio or PWM in, but there are many SMPS drivers out there.... ?

International rectumfryer  also has some interesting ones.. (IRS2092, etc...)

Using such a driver is actually quite tempting, as my own approach is quite complex. But as said, they all introduce switching deadtime and that is a significant source of nonlinearity.

[r0d3z1]

STM32F334 can do 217ps.

I also vote for F334, I have already used it for the digital control of a DC/DC at 300khz, the resolution is quite impressive. HRTIM is not strightforward but it worth it.

[Siwastaja]

STM32F334 can do 217ps.

I also vote for F334, I have already used it for the digital control of a DC/DC at 300khz, the resolution is quite impressive. HRTIM is not strightforward but it worth it.

It's great, I like it, and IMHO HRTIM is more straightforward than most other STM32 peripherals... At least when considering the possibilities / ease of use ratio. It's not completely trivial, but it's very flexible, and its design isn't brainfucked. I have a feeling that had they copypasted one more slave timer with output module (6 instead of 5) it could have become even more widely usable.

[SteveyG]

The requirements from what I've read look a little steep, have you taken a step back to see if there is a general alternative for what you're trying to do?

IMO, when you start looking for such specialised parts, 90% of the time there is a different solution that avoids these rare/expensive items.

[tatus1969]

I also vote for F334, I have already used it for the digital control of a DC/DC at 300khz, the resolution is quite impressive. HRTIM is not strightforward but it worth it.

It's great, I like it, and IMHO HRTIM is more straightforward than most other STM32 peripherals... At least when considering the possibilities / ease of use ratio. It's not completely trivial, but it's very flexible, and its design isn't brainfucked. I have a feeling that had they copypasted one more slave timer with output module (6 instead of 5) it could have become even more widely usable.

Now that I know that I will need at least 20bits DAC resolution, any kind of HRTIM is out. The audio DAC will very likely do that job.

The requirements from what I've read look a little steep, have you taken a step back to see if there is a general alternative for what you're trying to do?

I mentioned earlier, there is professional gear that does what my system is doing - starting at USD8000. I am collaborating with a large technical uni that has these instruments, and they are making comparison measurements right now. The first results look very promising 

IMO, when you start looking for such specialised parts, 90% of the time there is a different solution that avoids these rare/expensive items.

I try to avoid that wherever possible, as I know the availability nightmare that I would steer myself into when in mass production. At the moment, it is only special with regards to the microcontroller, an audio DAC, and some fast comparators and precision opamps [EDIT: plus SI8423 iso drivers].

[Siwastaja]

Li-ion battery AC analysis? 

[tatus1969]

Li-ion battery AC analysis? 

Sorry, I can't disclouse at the moment what it is intended for. I need a few months to build prototypes that I can show here or maybe even sell. They will have a documented control interface (and open source USB library) that will allow many different applications, for example plotting the voltage/capacitance dependency of high capacitance MLCC capacitors. I plan to keep hardware and firmware confidential though, as I think that Chinese copying will be a major thing.

I just found the source of the excessive measurement noise that I posted a picture of earlier. It was not (only) insufficient DAC resolution, but rather the algorithm that computes the sinusodial waveform. Updating this at 900kHz and using only a 32-bit integer for the phase is *not* sufficient to computer a 10Hz sine wave. Upgraded to 64 bits, working perfectly now.

[Yansi]

International rectumfryer  also has some interesting ones.. (IRS2092, etc...)

Using such a driver is actually quite tempting, as my own approach is quite complex. But as said, they all introduce switching deadtime and that is a significant source of nonlinearity.

But they DO NOT use strict constant frequency PWM as their modulation scheme. PWM modulation is plain bad in the first case.

Deadtime  is part of the feedback loop. Look closely how those drivers work. They integrate the output voltage, deadtime is pretty much cancelled out. You better worry about the linearity of the output filter.

[tatus1969]

International rectumfryer  also has some interesting ones.. (IRS2092, etc...)

Using such a driver is actually quite tempting, as my own approach is quite complex. But as said, they all introduce switching deadtime and that is a significant source of nonlinearity.

But they DO NOT use strict constant frequency PWM as their modulation scheme. PWM modulation is plain bad in the first case.

Deadtime  is part of the feedback loop. Look closely how those drivers work. They integrate the output voltage, deadtime is pretty much cancelled out. You better worry about the linearity of the output filter.

Similar to classical linear amps, avoiding nonlinearity in the first place gives the feedback opamp less work to do and improves THD. You can consider my approach being a combination of class A and class D.

[tatus1969]

Thinking about sigma delta modulation for the power amplifier... I'll need a clock in the order of 10MHz or higher. A first order SD modulator will then cause the H bridge to switch at the same rate, which will cause way too much power dissipation due to switching loss. I need to keep that below 500kHz. I don't see a simple way to reduce the frequency content of the generated bit stream, although there seem to be a few approaches. I see myself ending up adding an FPGA to the system to model that (although that would also eliminate the DAC). Also, sigma delta introduces quantization noise that pure analog PWM doesn't have.

I've also looked into self-oscillating topologies aka Bruno Putzey / UcD. It appears that these do not follow the input signal well according to my first ballpark simulations (picture). This leads me to think that I would either get too much load dependency and thus nonlinearity, or need to add another global feedback loop.

I think that I will revert to analog PWM with linearization feedback tapped at H bridge. Other than with the UcD approach, the output filters cannot be part of this feedback because that will cause instability with low impedance loads. I plan to make the LC filters as linear as possible instead, by overdimensioning L, and using voltage independent film capacitors.

Guys, does this sound reasonable?

[Yansi]

Why don't you try the second order modulator, as presented by me above? (IRS2092 for example, being a cheap integrated solution of that).  There is a ton of application notes about it, including implementing these from discrete components.

The strange circuit in your last post is well known to misbehave. (I have tried bulding several amplifiers with this principle, with not that much of a success) I think that self-oscillating structure (feedback after the LC filter) was patented by Philips few decades ago, but not certainly sure - please correct me if anyone knows exactly.

I do not think you can make a single ended class-D much better than that second order modulator. The principle is industry-wide accepted and used across multiple brands power amplifiers.

I think there is a good reason why straight PWM is not used and sigma-delta isn't any good either, due to the switching loss as you have correctly identified.

[tatus1969]

Why don't you try the second order modulator, as presented by me above? (IRS2092 for example, being a cheap integrated solution of that).  There is a ton of application notes about it, including implementing these from discrete components.

I've tried to model the IRS2092 (which is a poor mans 2nd order self oscillating sigma delta if I see this correctly) but could'nt make it to work as it should. I then created a 1st order model from scratch, which works as it should. Is there any benefit of a 2nd order modulator in my situation?

I had to realize again that sigma delta is not an option for me. I can't afford a high ratio of switching frequency to input frequency (that would allow clocked sd modulators), and I also can't work with the reduced switching speed of the self oscillating modulatorat high excursions. This is because I have to set the output filter cutoff frequency to at least 50kHz. And I have to use high Q LC filters that get overly excited in this situation. This brings me back to PWM and Putzeys being the only options. I'll keep you updated 

[mrflibble]

STM32F334 can do 217ps.

Oooh, nice! Didn't know that one yet. Guess what disco/nucleo board I will use to pad the next Mouser or Digikey order?

Also, minor nitpick: according to the datasheet that F334 runs at a boring clock rate of 144 MHz and does not have any 4.6 GHz bits in it (as a previous post would seem to suggest). That would have been an interesting waste of process technology if it did. 

I had to realize again that sigma delta is not an option for me. I can't afford a high ratio of switching frequency to input frequency (that would allow clocked sd modulators), and I also can't work with the reduced switching speed of the self oscillating modulatorat high excursions.

Delta-sigma does not automatically means that your output stage has to toggle at the same rate as your internal stages. You can use a multi-bit quantizer, and let that n-bit result be the PWM value for that period. So an example would be to have an internal rate of 1.280 MHz, but with a 6-bit quantizer. Which would translate to a 6-bit PWM with a toggle rate of 20 kHz on your 666 nC gatecharge mosfets, thus keeping those evil switching losses at an acceptable level.

Also, are all topologies (CIFF, CIFB, etc) a no-no, or just some? Anyways, even if you end up with straightup PWM for whatever top-secret reason, I would suggest you add some properly scaled pseudo-random noise at the quantizer stage. The bad stuff: raised noise floor. The good stuff: those pesky spurs at harmonics of your PWM frequency are waaay down. Cannot speak for your application, but so far in every case I had to make the call the advantages of the added PRNG far outweighed any drawbacks. And the PRNG doesn't even have to be fancy. At first I expended entirely too much time & effort making sure those random bits were nicely polished high quality random bits. Only to find out after more experimentation that any old LFSR would do just fine. You just have to make sure the LFSR period is sufficiently large for the given application, but that constraint is trivially met.

Minor suggestion: it might help if you could provide a minimal spice schematic of the load. No need to divulge what kind of top secret thingy you are trying to build. Just model the nasty difficult to drive aspects of the load. And if you are targeting a variety of loads, then lets say the top 3 nasty loads. Basically, take a bunch of R,L,C's, put in representative configurations. Then given those configurations, for what ranges of R,L,C values are you trying to do whatever it is you are trying to do. If that is already a top secret it's kind of difficult to give meaningful suggestions other than "Use delta-sigma, it's awesome!".

[Siwastaja]

Also, minor nitpick: according to the datasheet that F334 runs at a boring clock rate of 144 MHz and does not have any 4.6 GHz bits in it (as a previous post would seem to suggest). That would have been an interesting waste of process technology if it did. 

The HRTIM output generation counters run at 4.6GHz equivalent (yes, that's on the front page of the datasheet). Equivalent, because it isn't an actual binary digital counter; it's not clocked on an actual digital 4.6GHz square wave clock signal. Instead, it's some sort of analog implementation, and it runs self-calibration constantly against varying operating conditions. The key point is, it can time your output changes with 1/4.6GHz intervals, and it's presented to the programmer like it was a digital counter clocked from a 4.6GHz signal (but, unsuprisingly, with more jitter, and the step sizes probably showing slight non-linearity). There are some extra limitations for minimum pulse width as well.

[jmelson]

For an instrument that I am desigining, I need a PWM at 450kHz with good linearity and resolution (equivalent to at least 14 bits).

Hmmm, the totally simple way to do this has a counter running at 7.37 GHz.  This sounds QUITE challenging!

There possibly could be some solution with SERDES moduies on a FPGA with phase-shifted clocks.

But, sounds like a very tough problem.

Jon

[PCB.Wiz]

The HRTIM output generation counters run at 4.6GHz equivalent (yes, that's on the front page of the datasheet). Equivalent, because it isn't an actual binary digital counter; it's not clocked on an actual digital 4.6GHz square wave clock signal. Instead, it's some sort of analog implementation, and it runs self-calibration constantly against varying operating conditions. The key point is, it can time your output changes with 1/4.6GHz intervals, and it's presented to the programmer like it was a digital counter clocked from a 4.6GHz signal (but, unsuprisingly, with more jitter, and the step sizes probably showing slight non-linearity). There are some extra limitations for minimum pulse width as well.

Yes, the simplest way to get deep sub-ns is to use CMOS gate delay lines, (just tapped chains of gates) - very simple, but they do vary with Vcc and temperature, hence the calibration step most mention.
I've seen one Sanken MCU part that did a 1GHz PLL for a 1ns counter based PWM. (Not cheap and niche ...)

[tatus1969]

Hmmm, the totally simple way to do this has a counter running at 7.37 GHz.  This sounds QUITE challenging!

There possibly could be some solution with SERDES moduies on a FPGA with phase-shifted clocks.

But, sounds like a very tough problem.

I have moved to an analog solution, and a 192kHz / 24 bit sigma delta audio DAC will deliver enough resolution without having to deal with (quasi) GHz timers.

Delta-sigma does not automatically means that your output stage has to toggle at the same rate as your internal stages. You can use a multi-bit quantizer, and let that n-bit result be the PWM value for that period.

That sounds actually very interesting, and may be worth the necessary FPGA between MCU and power stage. I'm on a starting-to-learn-beginner level with respect to sigma delta, may I ask some questions?
- that approach above would result in a constant-frequency PWM, but I can imagine that a more complex mapping from multi-bit SD state to ON / OFF periods could allow for some frequency spreading that would help EMI. I have no practical idea of that though.
- when moving from an all analog PWM duty cycle at 500kHz to this time discrete solution, wouldn't I have to increase power stage switching frequency significantly?
- do I understand your proposal correctly that it would require a multi-bit DAC, or have you thought of an alll digital solution? In the latter case, I have no possibility to create linearization feedback from the power stage. In the earlier case, I would expect to introduce DAC nonlinearity, and would need some kind of low pass filtering.
- when going that route, what is the actual benefit that I can expect over a PWM?

PWM for whatever top-secret reason

That top-secret reasons are
- lack of profound knowledge of sigma delta modeling.
- wanting to make a solution with basic discrete components because of availability, price, and flexibility. If I would jump on integrated solutions like IRS2092, there's not much to tweak if that misbehaves.
- the demonstrator has already proven feasibility, the only identified problems were amplifier linearity when having to drive milliohm loads, and output filter oscillations because of dropping switching frequency when approaching the voltage rails.

Also, are all topologies (CIFF, CIFB, etc) a no-no, or just some?

There are no no-no's, I'm open to everything that will help. So far the only topologie that seems to be able to meet my goals is DAC + analog PWM + low-deadtime power stage + moderate feedback before the output filters + overdimensioned output filters.

pesky spurs at harmonics of your PWM frequency

I know what you mean. My last visit in the EMC chamber at our local TÜV office was a big fail - 30db above the limit. That should be solved now, fingers crossed for my next visit. Luckily this application requires multi-stage output filtering anyway and the final system will be metal enclosed.

model the nasty difficult to drive aspects of the load

I'd say, a typical representation of the worst case load is a voltage source of 2 to 25V, with a 1 milliOhm resistor at it's output. My instrument then has to drive current into that resistor, with that current having DC and AC amplitudes of up to +/- 5A with frequencies from 1mHz to 50kHz.

[nctnico]

So it is a battery analyser. That means the output swing (in voltage) is actually very low and so is the power. I think you are going at this the wrong way entirely. I have designed/made similar devices (some that needed to go up to 300VDC) and I always used a capacitor in series with the current source to get rid of the DC offset (with a fast settling circuit at startup). That way you can use a simple but precisely controlled linear current source. Since you'll be measuring the AC voltage across the battery and the AC current through it any voltage drop across the capacitor won't matter as long a the current source doesn't go outside it's output voltage. Another problem I see it resolution. If you have 14bit to go up to 25V then you'll have 1.5mV per bit. With a 1m Ohm resistor as a load you'll have very few bits left to construct a clean AC waveform. Unless you do some hefty filtering but the filter characteristic itself will also depend on the load. Either way at low frequencies you'll be applying a stepped waveform instead of a (somewhat) pure sine.

[tatus1969]

measuring the AC voltage across the battery and the AC current through it any voltage drop across the capacitor won't matter as long a the current source doesn't go outside it's output voltage.

What capacitor should that be that can couple 5A AC at 1mHz? For the same reason, I also can't use a transformer.

Another problem I see it resolution. If you have 14bit to go up to 25V then you'll have 1.5mV per bit.

I've noticed this mistake in an earlier post and upgraded to 24 bits.

EDIT:

the output swing (in voltage) is actually very low

That's not always true. That 1mOhm load was meant to describe the worst case situation for the amplifier. I also need to be able to deliver full 1 to 27V DC and AC for higher impedance loads.

[nctnico]

You can always consider a hybrid system where you have a charger & dc load for the low frequencies and a typical LCR meter circuit for the higher frequencies. This will greatly simplify your system.

A ceramic or polyester film capacitor can handle quite a bit of current as long as the ESR isn't causing problems. In a typical half-bridge forward converter (like any PC power supply) the current through the bridge is fed through a capacitor to prevent DC current through the core. Depending on the impedance of the measurement system you use 10uF to 100uF should get you in the single digit Hertz range.  I recommend using a PET capacitor because these have an ultra low leakage current.