hamster_nz, how do you debugged/made your implementation work? I am having some trouble with my implementation. When I look on modelsim, everything seem fine, got data in the right order. But when testing it in real life, nothing happen in wireshark. Not sure if it's a clock problem, crc problem, or data alignment with clock problem.
Hi,
My test setup is
- Nexys Video Board
- UTP cable
- Gigabit NIC on my laptop.
- Wireshark running under Windows 8 to capture the packets
I have to set the NIC on the laptop to 1Gb/Full Duplex, and then download the design.
Because the packets are not addressed directly to my laptop I don't seen any network bandwidth until I start capturing them.
Under windows you can use "netstat -e" to verify packet counts and look for FCS/checksum issues (bad CRCs increment to the 'error' counter).
Problems I could expect
- My board's PHY is strapped to be 10/100/1000 after reset. Yours may not be, and you may need to configure it through the serial management interface.
- In my HDL design the TX clk is at 90 degrees to the main logic's clock used for the data. Some phys have the option to insert delays on the clocking making 0 degrees the best.
- If it is your own code, the nibble ordering is painful and seems wrong. For example with a MAC of 01:23:45:67:89:AB it should hit the wire in this order 1,0,3,2,5,4,7,6,9,8,B,A.
If you need me to send any simulation traces or CRCs for test data pop me an PM with your email and what would help and I'll do what I can to help, or send me through some simulation traces and I'll take a look.